220 lines
9.7 KiB
Tcl
220 lines
9.7 KiB
Tcl
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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set adc_fifo_name axi_ad9625_fifo
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set adc_data_width 512
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set adc_dma_data_width 64
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# adc peripherals
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ad_ip_instance util_adxcvr util_fmcadc5_0_xcvr
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.CPLL_FBDIV 1
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.CPLL_FBDIV_4_5 5
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.TX_NUM_OF_LANES 0
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_NUM_OF_LANES 8
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_OUT_DIV 1
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_CLK25_DIV 25
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_PMA_CFG 0x00018480
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ad_ip_parameter util_fmcadc5_0_xcvr CONFIG.RX_CDR_CFG 0x03000023ff10200020
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ad_ip_instance util_adxcvr util_fmcadc5_1_xcvr
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.CPLL_FBDIV 1
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.CPLL_FBDIV_4_5 5
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.TX_NUM_OF_LANES 0
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_NUM_OF_LANES 8
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_OUT_DIV 1
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_CLK25_DIV 25
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_PMA_CFG 0x00018480
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ad_ip_parameter util_fmcadc5_1_xcvr CONFIG.RX_CDR_CFG 0x03000023ff10200020
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ad_ip_instance axi_adxcvr axi_ad9625_0_xcvr
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.ID 0
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.NUM_OF_LANES 8
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.LPM_OR_DFE_N 1
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.SYS_CLK_SEL 0x0
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ad_ip_parameter axi_ad9625_0_xcvr CONFIG.OUT_CLK_SEL 0x2
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ad_ip_instance axi_adxcvr axi_ad9625_1_xcvr
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.ID 1
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.NUM_OF_LANES 8
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.LPM_OR_DFE_N 1
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.SYS_CLK_SEL 0x0
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ad_ip_parameter axi_ad9625_1_xcvr CONFIG.OUT_CLK_SEL 0x2
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adi_axi_jesd204_rx_create axi_ad9625_0_jesd 8
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ad_ip_parameter axi_ad9625_0_jesd/rx CONFIG.SYSREF_IOB false
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adi_axi_jesd204_rx_create axi_ad9625_1_jesd 8
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ad_ip_parameter axi_ad9625_1_jesd/rx CONFIG.SYSREF_IOB false
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ad_ip_instance axi_ad9625 axi_ad9625_0_core
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ad_ip_parameter axi_ad9625_0_core CONFIG.ID 0
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ad_ip_instance axi_ad9625 axi_ad9625_1_core
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ad_ip_parameter axi_ad9625_1_core CONFIG.ID 1
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ad_ip_instance axi_dmac axi_ad9625_dma
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad9625_dma CONFIG.ID 0
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ad_ip_parameter axi_ad9625_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9625_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9625_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9625_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
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# reference clocks & resets
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create_bd_port -dir I rx_ref_clk_0
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create_bd_port -dir I rx_ref_clk_1
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ad_xcvrpll rx_ref_clk_0 util_fmcadc5_0_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_0 util_fmcadc5_0_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9625_0_xcvr/up_pll_rst util_fmcadc5_0_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9625_0_xcvr/up_pll_rst util_fmcadc5_0_xcvr/up_cpll_rst_*
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ad_xcvrpll rx_ref_clk_1 util_fmcadc5_1_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_1 util_fmcadc5_1_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_cpll_rst_*
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ad_connect sys_cpu_resetn util_fmcadc5_0_xcvr/up_rstn
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ad_connect sys_cpu_resetn util_fmcadc5_1_xcvr/up_rstn
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ad_connect sys_cpu_clk util_fmcadc5_0_xcvr/up_clk
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ad_connect sys_cpu_clk util_fmcadc5_1_xcvr/up_clk
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# connections (adc)
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ad_xcvrcon util_fmcadc5_0_xcvr axi_ad9625_0_xcvr axi_ad9625_0_jesd
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ad_xcvrcon util_fmcadc5_1_xcvr axi_ad9625_1_xcvr axi_ad9625_1_jesd
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins util_fmcadc5_1_xcvr/rx_out_clk_0]]
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delete_bd_objs [get_bd_nets -of_objects [get_bd_pins axi_ad9625_1_jesd_rstgen/peripheral_reset]]
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delete_bd_objs [get_bd_cells axi_ad9625_1_jesd_rstgen]
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ad_xcvrpll util_fmcadc5_0_xcvr/rx_out_clk_0 util_fmcadc5_1_xcvr/rx_clk_*
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_jesd/device_clk
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_0_core/rx_clk
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ad_connect axi_ad9625_0_jesd/rx_sof axi_ad9625_0_core/rx_sof
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ad_connect axi_ad9625_0_jesd/rx_data_tdata axi_ad9625_0_core/rx_data
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_core/rx_clk
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ad_connect axi_ad9625_0_jesd/rx_sof axi_ad9625_1_core/rx_sof
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ad_connect axi_ad9625_1_jesd/rx_data_tdata axi_ad9625_1_core/rx_data
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ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_0_core/adc_raddr_in
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ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_1_core/adc_raddr_in
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_fifo/adc_clk
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ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
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ad_connect axi_ad9625_fifo/adc_wovf axi_ad9625_0_core/adc_dovf
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ad_connect axi_ad9625_fifo/adc_wovf axi_ad9625_1_core/adc_dovf
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ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
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ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
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ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
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ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
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ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
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ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
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# interconnect (cpu)
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ad_cpu_interconnect 0x44a60000 axi_ad9625_0_xcvr
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ad_cpu_interconnect 0x44b60000 axi_ad9625_1_xcvr
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ad_cpu_interconnect 0x44a10000 axi_ad9625_0_core
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ad_cpu_interconnect 0x44b10000 axi_ad9625_1_core
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ad_cpu_interconnect 0x44a90000 axi_ad9625_0_jesd
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ad_cpu_interconnect 0x44b90000 axi_ad9625_1_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
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# interconnect (gt/adc)
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ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_0_xcvr/m_axi
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ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_1_xcvr/m_axi
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ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-12 mb-12 axi_ad9625_dma/irq
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ad_cpu_interrupt ps-11 mb-13 axi_ad9625_0_jesd/irq
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ad_cpu_interrupt ps-10 mb-14 axi_ad9625_1_jesd/irq
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# interleave-sync
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ad_disconnect rx_sysref_0 axi_ad9625_0_jesd/sysref
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ad_disconnect rx_sync_0 axi_ad9625_0_jesd/sync
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ad_disconnect rx_sysref_1_0 axi_ad9625_1_jesd/sysref
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ad_disconnect rx_sync_1_0 axi_ad9625_1_jesd/sync
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ad_disconnect spi_csn_o axi_spi/ss_o
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ad_disconnect spi_csn_i axi_spi/ss_i
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ad_disconnect spi_clk_i axi_spi/sck_i
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ad_disconnect spi_clk_o axi_spi/sck_o
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ad_disconnect spi_sdo_i axi_spi/io0_i
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ad_disconnect spi_sdo_o axi_spi/io0_o
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ad_disconnect spi_sdi_i axi_spi/io1_i
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ad_ip_instance axi_fmcadc5_sync axi_fmcadc5_sync
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ad_cpu_interconnect 0x44a20000 axi_fmcadc5_sync
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ad_connect sys_cpu_reset axi_fmcadc5_sync/delay_rst
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ad_connect sys_200m_clk axi_fmcadc5_sync/delay_clk
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ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_fmcadc5_sync/rx_clk
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ad_connect axi_ad9625_0_core/adc_enable axi_fmcadc5_sync/rx_enable_0
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ad_connect axi_ad9625_0_core/adc_data axi_fmcadc5_sync/rx_data_0
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ad_connect axi_ad9625_1_core/adc_enable axi_fmcadc5_sync/rx_enable_1
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ad_connect axi_ad9625_1_core/adc_data axi_fmcadc5_sync/rx_data_1
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ad_connect axi_fmcadc5_sync/rx_enable axi_ad9625_fifo/adc_wr
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ad_connect axi_fmcadc5_sync/rx_data axi_ad9625_fifo/adc_wdata
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ad_connect axi_fmcadc5_sync/rx_sysref axi_ad9625_0_jesd/sysref
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ad_connect axi_ad9625_0_jesd/sync axi_fmcadc5_sync/rx_sync_0
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ad_connect axi_fmcadc5_sync/rx_sysref axi_ad9625_1_jesd/sysref
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ad_connect axi_ad9625_1_jesd/sync axi_fmcadc5_sync/rx_sync_1
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ad_connect axi_spi/ss_o axi_fmcadc5_sync/spi_csn_o
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ad_connect axi_spi/sck_o axi_fmcadc5_sync/spi_clk_o
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ad_connect axi_spi/io0_o axi_fmcadc5_sync/spi_sdo_o
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ad_connect axi_spi/ss_i GND
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ad_connect axi_spi/sck_i GND
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ad_connect axi_spi/io0_i GND
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create_bd_port -dir O rx_sysref_p
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create_bd_port -dir O rx_sysref_n
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create_bd_port -dir O rx_sync_0_p
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create_bd_port -dir O rx_sync_0_n
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create_bd_port -dir O rx_sync_1_p
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create_bd_port -dir O rx_sync_1_n
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create_bd_port -dir O -from 7 -to 0 spi_csn
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create_bd_port -dir O spi_clk
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create_bd_port -dir O spi_mosi
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create_bd_port -dir I spi_miso
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create_bd_port -dir O psync
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create_bd_port -dir O vcal
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ad_connect axi_fmcadc5_sync/rx_sysref_p rx_sysref_p
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ad_connect axi_fmcadc5_sync/rx_sysref_n rx_sysref_n
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ad_connect axi_fmcadc5_sync/rx_sync_0_p rx_sync_0_p
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ad_connect axi_fmcadc5_sync/rx_sync_0_n rx_sync_0_n
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ad_connect axi_fmcadc5_sync/rx_sync_1_p rx_sync_1_p
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ad_connect axi_fmcadc5_sync/rx_sync_1_n rx_sync_1_n
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ad_connect axi_fmcadc5_sync/psync psync
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ad_connect axi_fmcadc5_sync/vcal vcal
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ad_connect axi_fmcadc5_sync/spi_csn spi_csn
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ad_connect axi_fmcadc5_sync/spi_clk spi_clk
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ad_connect axi_fmcadc5_sync/spi_mosi spi_mosi
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ad_connect spi_miso axi_fmcadc5_sync/spi_miso
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ad_connect spi_miso axi_spi/io1_i
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# Connect core_reset_ext to be used for synchronization
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create_bd_pin -dir I axi_ad9625_0_jesd/core_reset_ext
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create_bd_pin -dir I axi_ad9625_1_jesd/core_reset_ext
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ad_connect axi_ad9625_0_jesd/core_reset_ext axi_ad9625_0_jesd/rx_axi/core_reset_ext
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ad_connect axi_ad9625_1_jesd/core_reset_ext axi_ad9625_1_jesd/rx_axi/core_reset_ext
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ad_connect axi_ad9625_0_core/adc_rst axi_ad9625_0_jesd/core_reset_ext
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ad_connect axi_ad9625_0_core/adc_rst axi_ad9625_1_jesd/core_reset_ext
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