71469490c6
The read and write interfaces of a AXI bus are independent other than that they use the same clock. Yet when connecting a single read-only and a single write-only interface to a Xilinx AXI interconnect it instantiates arbitration logic between the two interfaces. This is dead logic and unnecessarily utilizes the FPGAs resources. Introduce a new helper module that takes a read-only and a write-only AXI interface and combines them into a single read-write interface. The only restriction here is that all three interfaces need to use the same clock. This module is useful for systems which feature a read DMA and a write DMA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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