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pluto_hdl_adi/library/xilinx/axi_dacfifo
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Istvan Csomortani 7340d8aa16 axi_dacfifo: DAC side CDC fifo control update 
The fifo will ask for a new data from the DDR, if the current
level is lower than the high threshold. This will prevent overflow.
By deleting the lower threshold, we can avoid ocassional underflows,
when the DAC rate is closer to the max DDRx rate.
 		2017-07-06 10:01:27 +01:00
..
Makefile hdlmake updates 2017-04-25 15:46:26 -04:00
axi_dacfifo.v axi_dacfifo: Fix the dma_ready signal generation 2017-07-06 10:01:17 +01:00
axi_dacfifo_constr.sdc adc/dac-fifo altera cores 2017-02-28 13:30:50 -05:00
axi_dacfifo_constr.xdc constraints: Update constraints 2017-02-24 13:43:32 +02:00
axi_dacfifo_dac.v axi_dacfifo: DAC side CDC fifo control update 2017-07-06 10:01:27 +01:00
axi_dacfifo_hw.tcl altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_dacfifo_ip.tcl axi_dacfifo: Add gray coder/decoder module 2017-07-06 10:01:27 +01:00
axi_dacfifo_rd.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
axi_dacfifo_wr.v axi_dacfifo: Add gray coder/decoder module 2017-07-06 10:01:27 +01:00