David Winter 73468d662b axi_tdd: Add false paths to tdd sync input ... This allows the external synchronization input to be driven from asynchronous sources like a 1 PPS signal or just signals from different clock domains in general. Signed-off-by: David Winter <david.winter@analog.com>		2022-04-20 10:54:53 +03:00
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Makefile	Makefile: Fix misc makefiles from projects and library	2021-10-05 14:24:48 +03:00
axi_tdd.v	axi_tdd: Add standalone axi_tdd IP core	2021-06-26 08:27:54 +03:00
axi_tdd_constr.xdc	axi_tdd: Add false paths to tdd sync input	2022-04-20 10:54:53 +03:00
axi_tdd_ip.tcl	library: Add link to wiki for IPs	2021-10-25 10:44:53 +03:00