109 lines
3.5 KiB
Verilog
109 lines
3.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// Transmit HDMI, RGB to CrYCb conversion
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// The multiplication coefficients are in 1.4.12 format
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// The addition coefficients are in 1.12.12 format
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// Cr = (+112.439/256)*R + (-094.154/256)*G + (-018.285/256)*B + 128;
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// Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16;
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// Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128;
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`timescale 1ns/100ps
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module ad_csc_RGB2CrYCb #(
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parameter DELAY_DATA_WIDTH = 16
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) (
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// R-G-B inputs
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input clk,
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input [DELAY_DATA_WIDTH-1:0] RGB_sync,
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input [23:0] RGB_data,
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// Cr-Y-Cb outputs
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output [DELAY_DATA_WIDTH-1:0] CrYCb_sync,
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output [23:0] CrYCb_data
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);
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localparam DW = DELAY_DATA_WIDTH - 1;
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// Cr (red-diff)
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ad_csc #(
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.DELAY_DW(DELAY_DATA_WIDTH)
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) j_csc_1_Cr (
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.clk (clk),
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.sync (RGB_sync),
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.data (RGB_data),
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.C1 ( 17'd28784), // 112.439
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.C2 (-17'd24103), // -94.154
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.C3 (-17'd4681), // -18.285
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.C4 ( 24'd8388608), // 128
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.csc_sync (CrYCb_sync),
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.csc_data (CrYCb_data[23:16]));
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// Y (luma)
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ad_csc #(
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.DELAY_DW(0)
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) j_csc_1_Y (
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.clk (clk),
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.sync (1'd0),
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.data (RGB_data),
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.C1 (17'd16829), // 65.739
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.C2 (17'd33039), // 129.057
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.C3 (17'd6416), // 25.064
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.C4 (24'd1048576), // 16
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.csc_sync (),
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.csc_data (CrYCb_data[15:8]));
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// Cb (blue-diff)
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ad_csc #(
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.DELAY_DW(0)
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) j_csc_1_Cb (
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.clk (clk),
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.sync (1'd0),
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.data (RGB_data),
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.C1 (-17'd9714), // -37.945
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.C2 (-17'd19070), // -74.494
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.C3 ( 17'd28784), // 112.439
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.C4 (24'd8388608), // 128
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.csc_sync (),
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.csc_data (CrYCb_data[7:0]));
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endmodule
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