Adrian Costina 39ac29bb01 AD9361: Altera, modified address width so that all registers are accessible ... Modified qsys project with the new address span		2014-07-08 10:41:51 +03:00
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ad9467_fmc	ad9467 : initial checkin	2014-04-09 17:34:40 +03:00
ad9625_fmc	ad9625: register map updates	2014-07-03 14:30:03 -04:00
ad9625x2_fmc	ad9625x2_fmc: added multi-sync support	2014-06-12 15:45:35 -04:00
ad9671_fmc	global clock fix	2014-06-03 09:23:23 -04:00
ad9680_eval	daq2: initial checkin	2014-06-12 15:54:25 -04:00
adv7511	kcu105 pwr-good removed	2014-07-07 09:56:13 -04:00
common	kcu105 pwr-good removed	2014-07-07 09:56:13 -04:00
daq2	kcu105 pwr-good removed	2014-07-07 09:56:13 -04:00
fmcjesdadc1	a5soc: removed jtag master control	2014-07-01 12:27:37 -04:00
fmcomms1	fmcomms1: modified the fmcomms1_bd.tcl to make it compatible with latest wfifo	2014-04-14 17:04:04 +03:00
fmcomms2	AD9361: Altera, modified address width so that all registers are accessible	2014-07-08 10:41:51 +03:00
fmcomms5	fmcomms5/zc702: removed unused ila cores	2014-05-20 14:42:48 -04:00
motor_control	motor_control: Changed controller to PID controller. Some estetic changes	2014-04-28 17:57:51 +03:00
scripts	zc706-plddr3: read changes to lower dma clock	2014-06-25 09:20:58 -04:00
usdrx1	usdrx1: global clock fix	2014-06-10 18:09:49 +03:00