642 lines
13 KiB
Plaintext
642 lines
13 KiB
Plaintext
TITLE
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I3C Controller (i3c_controller_host_interface)
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i3c_controller_host_interface
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x00
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VERSION
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Version of the peripheral. Follows semantic versioning. Current version 0.01.00
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ENDREG
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FIELD
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[31:16] 0x00
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VERSION_MAJOR
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RO
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ENDFIELD
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FIELD
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[15:8] 0x01
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VERSION_MINOR
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RO
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ENDFIELD
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FIELD
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[7:0] 0x00
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VERSION_PATCH
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RO
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x01
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DEVICE_ID
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ENDREG
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FIELD
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[31:0] ''ID''
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DEVICE_ID
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RO
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Value of the ID configuration parameter.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x02
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SCRATCH
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ENDREG
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FIELD
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[31:0] 0x00000000
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SCRATCH
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RW
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Scratch register useful for debug.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x10
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ENABLE
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ENDREG
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FIELD
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[0] 0x1
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ENABLE
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RW
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Enable register. If the enable bit is set to 1 the internal state of the peripheral is reset.
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For proper operation, the bit needs to be set to 0.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x20
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IRQ_MASK
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ENDREG
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FIELD
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[7] 0x0
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DAA_PENDING
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RW
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If set to 0 the DAA_PENDING interrupt is masked.
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ENDFIELD
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FIELD
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[6] 0x0
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IBI_PENDING
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RW
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If set to 0 the IBI_PENDING interrupt is masked.
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ENDFIELD
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FIELD
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[5] 0x0
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CMDR_PENDING
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RW
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If set to 0 the CMDR_PENDING interrupt is masked.
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ENDFIELD
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FIELD
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[4] 0x0
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IBI_ALMOST_FULL
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RW
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If set to 0 the IBI_ALMOST_FULL interrupt is masked.
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ENDFIELD
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FIELD
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[3] 0x0
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SDI_ALMOST_FULL
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RW
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If set to 0 the SDI_ALMOST_FULL interrupt is masked.
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ENDFIELD
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FIELD
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[2] 0x0
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SDO_ALMOST_EMPTY
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RW
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If set to 0 the SDO_ALMOST_EMPTY interrupt is masked.
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ENDFIELD
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FIELD
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[1] 0x0
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CMDR_ALMOST_FULL
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RW
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If set to 0 the CMDR_ALMOST_FULL interrupt is masked.
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ENDFIELD
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FIELD
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[0] 0x0
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CMD_ALMOST_EMPTY
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RW
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If set to 0 the CMD_ALMOST_EMPTY interrupt is masked.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x21
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IRQ_PENDING
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ENDREG
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FIELD
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[31:0] 0x00000000
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IRQ_PENDING
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RW
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Pending IRQs with mask.
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Write 1 at the CMDR_PENDING bit to clear it.
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For CMDR_PENDING and IBI_PENDING, will be cleared if the FIFOs are also empty.
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For DAA_PENDING, will be cleared if the SDO FIFO is not empty, that means, got dynamic
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address in the pipeline.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x22
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IRQ_SOURCE
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ENDREG
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FIELD
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[31:0] 0x00000000
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IRQ_SOURCE
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RO
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Pending IRQs without mask.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x30
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CMD_FIFO_ROOM
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ENDREG
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FIELD
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[31:0] 0xXXXXXXXX
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CMD_FIFO_ROOM
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RO
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Number of free entries in the CMD FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x31
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CMDR_FIFO_LEVEL
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ENDREG
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FIELD
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[31:0] 0x00000000
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CMDR_FIFO_LEVEL
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RO
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Number of valid entries in the CMDR FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x32
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SDO_FIFO_ROOM
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ENDREG
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FIELD
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[31:0] 0xXXXXXXXX
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SDO_FIFO_ROOM
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RO
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Number of free entries in the SDO FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x33
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SDI_FIFO_LEVEL
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ENDREG
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FIELD
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[31:0] 0x00000000
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SDI_FIFO_LEVEL
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RO
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Number of valid entries in the serial-data-in FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x34
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IBI_FIFO_LEVEL
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ENDREG
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FIELD
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[31:0] 0x00000000
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IBI_FIFO_LEVEL
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RO
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Number of valid entries in the in-bus-interrupt FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x35
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CMD_FIFO
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Command FIFO register. Writing to this register inserts an entry into the CMD FIFO.
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Writing to this register when the CMD FIFO is full has no effect and the written entry
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is discarded. Reading from this register always returns 0x00000000.
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The Software is responsive for a valid sequence of commands.
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If the peripheral does not ACK when required during a command, the procedure exits and the
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next command in the FIFO is interpreted.
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See :ref:`i3c_controller instruction-format` for the structure of the command.
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ENDREG
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FIELD
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[22] 0xX
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CMD_IS_CCC
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WO
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Indicate if it is a CCC transfer (1) or not (0).
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ENDFIELD
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FIELD
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[21] 0xX
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CMD_BCAST_HEADER
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WO
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Include broadcast header in private transfer (1) or not (0).
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ENDFIELD
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FIELD
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[20] 0xX
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CMD_SR
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WO
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Repeated start flag, yield a Sr (1) or P (0) at the end of the transfer.
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ENDFIELD
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FIELD
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[19:8] 0xXXX
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CMD_BUFFER_LENGHT
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WO
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Unsigned 12-bits payload length, direction depends on RNW value.
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ENDFIELD
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FIELD
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[7:1] 0xXX
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CMD_DA
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WO
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7-bit device address (don’t care in broadcast mode).
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ENDFIELD
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FIELD
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[0] 0xX
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CMD_RNW
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WO
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If should retrieve data from device (1) or not (0).
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x36
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CMDR_FIFO
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CMDR FIFO register. Reading from this register removes the first entry from the CMDR FIFO.
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Reading this register when the CMDR FIFO is empty will return undefined data.
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Writing to it has no effect.
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ENDREG
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FIELD
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[23:0] 0x??
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CMDR_FIFO_ERROR
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RO
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If an error occurred during the transfer.
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ENDFIELD
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FIELD
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[19:8] 0x??
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CMDR_FIFO_BUFFER_LENGTH
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RO
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Unsigned 12-bits transferred payload length.
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ENDFIELD
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FIELD
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[7:0] 0x??
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CMDR_FIFO_SYNC
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RO
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Command synchronization.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x37
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SDO_FIFO
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SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO.
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Writing to this register when the SDO FIFO is full has no effect and the written entry
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is discarded. Reading from this register always returns 0x00000000.
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ENDREG
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FIELD
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[31:24] 0xXX
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SDO_FIFO_BYTE_3
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RO
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ENDFIELD
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FIELD
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[23:16] 0xXX
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SDO_FIFO_BYTE_2
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RO
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ENDFIELD
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FIELD
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[15:8] 0xXX
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SDO_FIFO_BYTE_1
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RO
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ENDFIELD
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FIELD
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[7:0] 0xXX
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SDO_FIFO_BYTE_0
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RO
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x38
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SDI_FIFO
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SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO.
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Reading this register when the SDI FIFO is empty will return undefined data.
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Writing to it has no effect.
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ENDREG
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FIELD
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[31:0] 0xXXXXXXXX
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SDI_FIFO
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RO
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x39
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IBI_FIFO
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IBI FIFO register. Reading from this register removes the first entry from the IBI FIFO.
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Reading this register when the IBI FIFO is empty will return undefined data.
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Writing to it has no effect.
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ENDREG
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FIELD
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[23:17] 0xXX
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IBI_FIFO_DA
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RO
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IBI Dynamic address.
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ENDFIELD
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FIELD
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[15:8] 0xXX
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IBI_FIFO_MDB
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RO
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IBI MDB, if the peripheral's BCR[2] is Low, the field is ignored.
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ENDFIELD
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FIELD
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[7:0] 0xXX
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IBI_FIFO_SYNC
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RO
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Synchronization number.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x3a
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FIFO_STATUS
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ENDREG
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FIELD
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[2] 0x1
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SDI_EMPTY
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RO
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If there is no element to be read in the SDI FIFO.
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ENDFIELD
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FIELD
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[1] 0x1
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IBI_EMPTY
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RO
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If there is no element to be read in the IBI FIFO.
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ENDFIELD
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FIELD
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[0] 0x1
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CMDR_EMPTY
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RO
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If there is no element to be read in the CMDR FIFO.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x40
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OPS
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Configure the operation of the controller.
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ENDREG
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FIELD
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[7] 0x0
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OPS_STATUS_NOP
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RO
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This bit is set to 1 when the bus is not executing any procedure.
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It is not idle bus condition since it set right after the Stop.
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ENDIELD
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FIELD
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[6:5] 0x0
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OPS_SPEED_GRADE
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RW
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Sets the speed grade in push-pull mode.
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Speed with 100MHz driver clock are:
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00: 1.56MHz (default)
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01: 3.12MHz
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10: 6.25MHz
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11: 12.50MHz
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ENDFIELD
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FIELD
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[4:1] 0x0
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OPS_OFFLOAD_LENGTH
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RW
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Offload commands length.
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ENDFIELD
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FIELD
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[0] 0x0
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OPS_MODE
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RW
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Set 0 to direct transfers, 1 to offload operation.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x50
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IBI_CONFIG
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Configure the In-Band Interrupt (IBI) feature.
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ENDREG
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FIELD
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[1] 0x0
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IBI_CONFIG_AUTO
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WO
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Set this bit to listen for IBI requests (when a peripheral pulls SDA Low during quiet times).
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After the IBI request is resolved, the controller returns to idle, since it is was not doing
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a cmd transfer.
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IBI_CONFIG_ENABLE must be set 1.
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ENDFIELD
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FIELD
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[0] 0x0
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IBI_CONFIG_ENABLE
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WO
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Set this bit to accept (ACK) IBI requests.
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If disabled, the controller will NACK IBI requests.
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If enabled, the controller will ACK the IBI request and receive the MDB.
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In both cases, the controller will proceed with the cmd transfer after resolving the IBI
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request.
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Accepted IBIs fill the IBI_FIFO and generate an interruption in the PS.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x60
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DEV_CHAR
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Holds devices characteristics that are looked-up during execution.
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The content is written only by software.
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To read an address, write the address with DEV_CHAR_0_WEN 0 and then read.
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ENDREG
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FIELD
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[15:9] 0x00
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DEV_CHAR_ADDR
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RW
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Device address to apply DEV_CHAR[3:0].
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ENDFIELD
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FIELD
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[8] 0xX
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DEV_CHAR_WEN
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W
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Enable write of the fields.
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ENDFIELD
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FIELD
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[3] 0x0
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DEV_CHAR_HAS_IBI_MDB
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RW
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Indicates if the device sends an MDB during the IBI.
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0 does not, 1 does.
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ENDFIELD
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FIELD
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[2] 0x0
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DEV_CHAR_IS_IBI_CAPABLE
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RW
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Indicates if the device can send IBI.
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0 does not, 1 does.
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ENDFIELD
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FIELD
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[1] 0x0
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DEV_CHAR_IS_ATTACHED
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RW
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Indicate if the device is attached.
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ENDFIELD
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[0] 0x0
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DEV_CHAR_IS_I2C
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RW
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Indicates if the device is I²C.
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0 is I3C device, 1 is I²C device.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0xb0 + 0x01*n
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OFFLOAD_CMD_n
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Offload command memory. Write commands in sequence to these addresses and update the
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OFFLOAD_CMD_LENGTH register.
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ENDREG
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FIELD
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[31:0] 0x00
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OFFLOAD_CMD
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RW
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The command to the I3C controller to execute.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0xc0 + 0x01*n
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OFFLOAD_SDO_n
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Offload SDO memory.
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Dual access memory sector used to store the SDO payload for the offload execution.
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The SDO is read by the parsing the OFFLOAD_CMD commands.
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For example, if the first command on OFFLOAD_CMD is a write with length 3 and the next with
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length 2, 3 bytes from OFFLOAD_SDO_0 are sent, then 2 bytes from OFFLOAD_SDO_1 are sent.
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If OPS_OFFLOAD_LENGTH is 2, then the burst concludes and the "pointer" resets to
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OFFLOAD_SDO_0, otherwise, the execution continues until all commands are resolved, always
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bounded by OPS_OFFLOAD_LENGTH.
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ENDREG
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FIELD
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[31:24] 0x00
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OFFLOAD_SDO_BYTE_3
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RO
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ENDFIELD
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FIELD
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[23:16] 0x00
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OFFLOAD_SDO_BYTE_2
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RO
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ENDFIELD
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FIELD
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[15:8] 0x00
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OFFLOAD_SDO_BYTE_1
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RO
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ENDFIELD
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FIELD
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[7:0] 0x00
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OFFLOAD_SDO_BYTE_0
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RO
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ENDFIELD
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############################################################################################
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############################################################################################
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