179 lines
5.0 KiB
Verilog
179 lines
5.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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input ref_clk_125_p,
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input ref_clk_125_n,
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// RGMII interface
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output reset_a,
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output mdc_fmc_a,
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inout mdio_fmc_a,
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input [3:0] rgmii_rxd_a,
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input rgmii_rx_ctl_a,
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input rgmii_rxc_a,
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output [3:0] rgmii_txd_a,
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output rgmii_tx_ctl_a,
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output rgmii_txc_a,
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input link_st_a,
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input int_n_a,
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input led_0_a,
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output reset_b,
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output mdc_fmc_b,
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inout mdio_fmc_b,
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input [3:0] rgmii_rxd_b,
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input rgmii_rx_ctl_b,
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input rgmii_rxc_b,
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output [3:0] rgmii_txd_b,
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output rgmii_tx_ctl_b,
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output rgmii_txc_b,
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input link_st_b,
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input int_n_b,
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input led_0_b,
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// LEDs
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output led_ar_c_c2m,
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output led_ar_a_c2m,
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output led_al_c_c2m,
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output led_al_a_c2m,
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output led_br_c_c2m,
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output led_br_a_c2m,
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output led_bl_c_c2m,
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output led_bl_a_c2m
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);
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// internal signals
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wire reset;
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wire [ 1:0] speed_mode_a_s;
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wire [ 1:0] speed_mode_b_s;
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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assign reset_a = reset;
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assign reset_b = reset;
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// port a - right led (activity/status) yellow only
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assign led_ar_c_c2m = led_0_a;
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assign led_ar_a_c2m = 1'b0;
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// port a - left led (speed mode): 10M=off, 100M=yellow, 1G=green
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assign led_al_c_c2m = speed_mode_a_s[0];
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assign led_al_a_c2m = speed_mode_a_s[1];
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// port b - right led (activity/status) yellow only
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assign led_br_c_c2m = led_0_b;
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assign led_br_a_c2m = 1'b0;
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// port a - left led (speed mode): 10M=off, 100M=yellow, 1G=green
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assign led_bl_c_c2m = speed_mode_b_s[0];
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assign led_bl_a_c2m = speed_mode_b_s[1];
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assign gpio_i[94:36] = gpio_o[94:36];
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assign gpio_i[35] = link_st_a;
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assign gpio_i[34] = link_st_b;
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assign gpio_i[33] = int_n_a;
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assign gpio_i[32] = int_n_b;
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assign gpio_i[31:21] = gpio_o[31:21];
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assign gpio_i[ 7:0] = gpio_o[7:0];
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assign gpio_bd_o = gpio_o[ 7:0];
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assign gpio_i[20:8] = gpio_bd_i;
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IBUFDS i_ibufds_sysref_1 (
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.I (ref_clk_125_p),
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.IB (ref_clk_125_n),
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.O (ref_clk_125));
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// instantiations
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (),
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.spi0_csn (),
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.spi0_miso (1'b0),
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.spi0_mosi (),
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.spi0_sclk (),
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.spi1_csn (),
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.spi1_miso (1'b0),
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.spi1_mosi (),
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.spi1_sclk (),
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.reset (reset),
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.clock_speed_0(),
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.MDIO_PHY_0_mdc (mdc_fmc_a),
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.MDIO_PHY_0_mdio_io (mdio_fmc_a),
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.RGMII_0_rd (rgmii_rxd_a),
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.RGMII_0_rx_ctl (rgmii_rx_ctl_a),
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.RGMII_0_rxc (rgmii_rxc_a),
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.RGMII_0_td (rgmii_txd_a),
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.RGMII_0_tx_ctl (rgmii_tx_ctl_a),
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.RGMII_0_txc (rgmii_txc_a),
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.ref_clk_125 (ref_clk_125),
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.speed_mode_a (speed_mode_a_s),
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.MDIO_PHY_1_mdc (mdc_fmc_b),
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.MDIO_PHY_1_mdio_io (mdio_fmc_b),
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.RGMII_1_rd (rgmii_rxd_b),
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.RGMII_1_rx_ctl (rgmii_rx_ctl_b),
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.RGMII_1_rxc (rgmii_rxc_b),
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.RGMII_1_td (rgmii_txd_b),
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.RGMII_1_tx_ctl (rgmii_tx_ctl_b),
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.RGMII_1_txc (rgmii_txc_b),
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.speed_mode_b (speed_mode_b_s));
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endmodule
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