Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables		2019-06-11 18:13:06 +03:00
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zc706_plddr3_adcfifo_bd.tcl	zc706/plddr3_adc|dacfifo_bd: PL DDR3 size is 1Gbyte	2019-05-06 17:17:00 +03:00
zc706_plddr3_constr.xdc	plddr3- change to board files	2017-02-22 15:22:50 -05:00
zc706_plddr3_dacfifo_bd.tcl	zc706/plddr3_adc|dacfifo_bd: PL DDR3 size is 1Gbyte	2019-05-06 17:17:00 +03:00
zc706_plddr3_mig.prj	plddr3- change to board files	2017-02-22 15:22:50 -05:00
zc706_system_bd.tcl	block_design: Updates with new reset net variables	2019-06-11 18:13:06 +03:00
zc706_system_constr.xdc	zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS	2019-05-30 14:55:11 +03:00