251 lines
7.6 KiB
Verilog
251 lines
7.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad7616_control (
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// control signals
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cnvst,
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busy,
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up_read_data,
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up_read_valid,
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up_write_data,
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up_read_req,
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up_write_req,
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up_burst_length,
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end_of_conv,
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// bus interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack
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);
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parameter ID = 0;
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parameter IF_TYPE = 0;
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localparam PCORE_VERSION = 'h0001001;
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localparam POS_EDGE = 0;
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localparam NEG_EDGE = 1;
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localparam SERIAL = 0;
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localparam PARALLEL = 1;
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output cnvst;
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input busy;
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output end_of_conv;
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output [ 4:0] up_burst_length;
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input [15:0] up_read_data;
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input up_read_valid;
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output [15:0] up_write_data;
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output up_read_req;
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output up_write_req;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [13:0] up_waddr;
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input [31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [13:0] up_raddr;
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output [31:0] up_rdata;
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output up_rack;
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// internal signals
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reg [31:0] up_scratch = 32'b0;
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reg up_resetn = 1'b0;
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reg up_cnvst_en = 1'b0;
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reg up_wack = 1'b0;
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reg up_rack = 1'b0;
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reg [31:0] up_rdata = 32'b0;
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reg [31:0] up_conv_rate = 32'b0;
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reg [ 4:0] up_burst_length = 5'h0;
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reg [15:0] up_write_data = 16'h0;
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reg [31:0] cnvst_counter = 32'b0;
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reg [ 3:0] pulse_counter = 8'b0;
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reg cnvst_buf = 1'b0;
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reg cnvst_pulse = 1'b0;
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reg [ 2:0] chsel_ff = 3'b0;
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wire up_rst;
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wire up_rreq_s;
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wire up_rack_s;
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wire up_wreq_s;
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wire [31:0] up_read_data_s;
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wire up_read_valid_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == 6'h01) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == 6'h01) ? up_rreq : 1'b0;
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// the up_[read/write]_data interfaces are valid just in parallel mode
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assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1;
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assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : {2{16'hDEAD}};
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 1'h0;
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up_scratch <= 32'b0;
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up_resetn <= 1'b0;
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up_cnvst_en <= 1'b0;
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up_conv_rate <= 32'b0;
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up_burst_length <= 5'h0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
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up_resetn <= up_wdata[0];
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up_cnvst_en <= up_wdata[1];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
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up_conv_rate <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
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up_burst_length <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
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up_write_data <= up_wdata;
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end
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end
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end
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assign up_write_req = (up_waddr[7:0] == 8'h14) ? up_wreq_s : 1'h0;
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// processor read interface
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assign up_rack_s = (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
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assign up_read_req = (up_raddr[7:0] == 8'h13) ? up_rreq_s : 1'b0;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 1'b0;
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up_rdata <= 32'b0;
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end else begin
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up_rack <= up_rack_s;
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if (up_rack_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h00 : up_rdata = PCORE_VERSION;
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8'h01 : up_rdata = ID;
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8'h02 : up_rdata = up_scratch;
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8'h03 : up_rdata = IF_TYPE;
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8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
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8'h11 : up_rdata = up_conv_rate;
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8'h12 : up_rdata = {27'b0, up_burst_length};
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8'h13 : up_rdata = up_read_data_s;
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endcase
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end
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end
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end
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// instantiations
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assign up_rst = ~up_rstn;
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ad_edge_detect #(
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.EDGE(NEG_EDGE)
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) i_ad_edge_detect (
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.clk (up_clk),
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.rst (up_rst),
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.in (busy),
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.out (end_of_conv)
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);
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// convertion start generator
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// NOTE: + The minimum convertion cycle is 1 us
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// + The rate of the cnvst must be defined in a way,
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// to not lose any data. cnvst_rate >= t_conversion + t_aquisition
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// See the AD7616 datasheet for more information.
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always @(posedge up_clk) begin
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if(up_resetn == 1'b0) begin
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cnvst_counter <= 32'b0;
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end else begin
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cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0;
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end
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end
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always @(cnvst_counter, up_conv_rate) begin
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cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0;
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end
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always @(posedge up_clk) begin
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if(up_resetn == 1'b0) begin
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pulse_counter <= 3'b0;
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cnvst_buf <= 1'b0;
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end else begin
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pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 3'b0;
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if(cnvst_pulse == 1'b1) begin
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cnvst_buf <= 1'b1;
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end else if (pulse_counter[2] == 1'b1) begin
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cnvst_buf <= 1'b0;
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end
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end
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end
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assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
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endmodule
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