pluto_hdl_adi

History

Istvan Csomortani 20c714eccf common: Define three global clock nets For all the Xilinx base design, define three global clock nets, which are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk and $sys_iodelay_clk. These clock nets are connected to different clock sources depending of the FPGA architecture used on the carrier. In general the following frequencies are used: - sys_cpu_clk - 100MHz - sys_dma_clk - 200MHz or 250Mhz - sys_iodelay_clk - 200MHz or 500Mhz	2019-06-11 18:13:06 +03:00
..
zed_system_bd.tcl	common: Define three global clock nets	2019-06-11 18:13:06 +03:00
zed_system_constr.xdc	zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS	2019-05-30 14:55:11 +03:00

Istvan Csomortani 20c714eccf common: Define three global clock nets

For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.

These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:

  - sys_cpu_clk     - 100MHz
  - sys_dma_clk     - 200MHz or 250Mhz
  - sys_iodelay_clk - 200MHz or 500Mhz

2019-06-11 18:13:06 +03:00

zed_system_bd.tcl

common: Define three global clock nets

2019-06-11 18:13:06 +03:00

zed_system_constr.xdc

zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS

2019-05-30 14:55:11 +03:00