134 lines
4.3 KiB
Verilog
134 lines
4.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module axi_register_slice (
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input clk,
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input resetn,
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input s_axi_valid,
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output s_axi_ready,
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input [DATA_WIDTH-1:0] s_axi_data,
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output m_axi_valid,
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input m_axi_ready,
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output [DATA_WIDTH-1:0] m_axi_data
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);
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parameter DATA_WIDTH = 32;
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parameter FORWARD_REGISTERED = 0;
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parameter BACKWARD_REGISTERED = 0;
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/*
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s_axi_data -> bwd_data -> fwd_data(1) -> m_axi_data
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s_axi_valid -> bwd_valid -> fwd_valid(1) -> m_axi_valid
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s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready
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(1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid
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(2) BACKWARD_REGISTERED insters a FF before s_axi_ready
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*/
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wire [DATA_WIDTH-1:0] bwd_data_s;
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wire bwd_valid_s;
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wire bwd_ready_s;
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wire [DATA_WIDTH-1:0] fwd_data_s;
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wire fwd_valid_s;
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wire fwd_ready_s;
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generate if (FORWARD_REGISTERED == 1) begin
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reg fwd_valid;
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reg [DATA_WIDTH-1:0] fwd_data;
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assign fwd_ready_s = ~fwd_valid | m_axi_ready;
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assign fwd_valid_s = fwd_valid;
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assign fwd_data_s = fwd_data;
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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fwd_valid <= 1'b0;
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end else begin
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if (~fwd_valid | m_axi_ready)
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fwd_data <= bwd_data_s;
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if (bwd_valid_s)
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fwd_valid <= 1'b1;
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else if (m_axi_ready)
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fwd_valid <= 1'b0;
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end
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end
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end else begin
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assign fwd_data_s = bwd_data_s;
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assign fwd_valid_s = bwd_valid_s;
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assign fwd_ready_s = m_axi_ready;
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end
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endgenerate
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generate if (BACKWARD_REGISTERED == 1) begin
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reg bwd_ready;
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reg [DATA_WIDTH-1:0] bwd_data;
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assign bwd_valid_s = ~bwd_ready | s_axi_valid;
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assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
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assign bwd_ready_s = bwd_ready;
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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bwd_ready <= 1'b1;
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end else begin
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if (bwd_ready)
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bwd_data <= s_axi_data;
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if (fwd_ready_s)
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bwd_ready <= 1'b1;
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else if (s_axi_valid)
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bwd_ready <= 1'b0;
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end
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end
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end else begin
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assign bwd_valid_s = s_axi_valid;
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assign bwd_data_s = s_axi_data;
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assign bwd_ready_s = fwd_ready_s;
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end endgenerate
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assign m_axi_data = fwd_data_s;
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assign m_axi_valid = fwd_valid_s;
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assign s_axi_ready = bwd_ready_s;
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endmodule
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