88 lines
3.1 KiB
Verilog
88 lines
3.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_adxcvr_mstatus (
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input up_rstn,
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input up_clk,
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input up_pll_locked_in,
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input up_rst_done_in,
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input up_pll_locked,
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input up_rst_done,
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output up_pll_locked_out,
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output up_rst_done_out);
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// parameters
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parameter integer XCVR_ID = 0;
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parameter integer NUM_OF_LANES = 8;
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// internal registers
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reg up_pll_locked_int = 'd0;
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reg up_rst_done_int = 'd0;
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// internal signals
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wire up_pll_locked_s;
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wire up_rst_done_s;
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// daisy-chain the signals
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assign up_pll_locked_out = up_pll_locked_int;
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assign up_rst_done_out = up_rst_done_int;
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assign up_pll_locked_s = (XCVR_ID < NUM_OF_LANES) ? up_pll_locked : 1'b1;
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assign up_rst_done_s = (XCVR_ID < NUM_OF_LANES) ? up_rst_done : 1'b1;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_pll_locked_int <= 1'd0;
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up_rst_done_int <= 1'd0;
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end else begin
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up_pll_locked_int <= up_pll_locked_in & up_pll_locked_s;
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up_rst_done_int <= up_rst_done_in & up_rst_done_s;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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