pluto_hdl_adi/library/xilinx/util_adxcvr
Lars-Peter Clausen f647dd4c0a xilinx: util_adxcvr: Add support for lane polarity inversion
Some designs choose to swap the positive and negative side of the of the
JESD204 lanes. One reason for this would be because it can simplify the
PCB layout. The polarity is in most cases also only applied to a subset of
the used lanes.

Add support for this to the util_adxcvr module. This done by adding new
parameter to the modules that allows to specify a per lane polarity
inversion. Each bit in the parameter corresponds to one lane. If the bit is
set the polarity is inverted for his lane. E.g. setting the parameter to
0xc will invert the 3rd and 4th lane.

The setting is forwarded to the Xilinx transceiver for the corresponding
lane.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 09:37:23 +02:00
..
Makefile Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
util_adxcvr.v xilinx: util_adxcvr: Add support for lane polarity inversion 2018-05-02 09:37:23 +02:00
util_adxcvr_constr.xdc constraints: Update constraints 2017-02-24 13:43:32 +02:00
util_adxcvr_ip.tcl util_adxcvr: Don't show reset ports for disabled lanes 2018-04-11 15:09:54 +03:00
util_adxcvr_xch.v xilinx: util_adxcvr: Add support for lane polarity inversion 2018-05-02 09:37:23 +02:00
util_adxcvr_xcm.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00