e2c75c015f
This change adds the TLAST signal to the AXI streaming interface of the source side for Intel targets. Xilinx based designs already have this since the tlast is part of the interface definition. In order to make the signal optional and let the tool connect a default value to the it, the USE_TLAST_SRC/DEST parameter is added to the configuration UI. This conditions the tlast port on the interface of the DMAC. Xilinx handles the optional signals much better so the parameter is not required there. |
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| .. | ||
| daq3_bd.tcl | ||
| daq3_qsys.tcl | ||
| daq3_spi.v | ||