132 lines
4.4 KiB
Verilog
132 lines
4.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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// The AD4630-24 device requires this module to capture data in master and
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// echo clock mode, because the data is clocked by the BUSY/SCLKOUT line,
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// independent from the SPI interface
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module ad463x_data_capture #(
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parameter DDR_EN = 0,
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parameter NUM_OF_LANES = 2,
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parameter DATA_WIDTH = 32
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) (
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input clk, // core clock of the SPIE
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input csn, // CSN (chip select)
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input echo_sclk, // BUSY/SCLKOUT
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input [NUM_OF_LANES-1:0] data_in, // serial data lines
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output [(NUM_OF_LANES * DATA_WIDTH)-1:0] m_axis_data, // parallel data lines
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output m_axis_valid, // data validation
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input m_axis_ready // NOTE: back pressure is ignored
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);
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reg csn_d;
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wire reset;
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always @(posedge clk) begin
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csn_d <= csn;
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end
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// negative edge resets the shift registers
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assign reset = ~csn & csn_d;
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// CSN positive edge validates the output data
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// WARNING: there isn't any buffering for data, if the sink module is not
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// ready, the data will be discarded
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assign m_axis_valid = csn & ~csn_d & m_axis_ready;
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genvar i, j;
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generate
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if (DDR_EN) // Double Data Rate mode
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begin
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for (i=0; i<NUM_OF_LANES; i=i+1) begin
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reg [DATA_WIDTH-1:0] data_shift_p;
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reg [DATA_WIDTH-1:0] data_shift_n;
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// shift register for positive edge
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always @(negedge echo_sclk or posedge reset) begin
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if (reset) begin
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data_shift_n <= 0;
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end else begin
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data_shift_n <= {data_shift_n, data_in[i]};
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end
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end
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// shift register for positive edge
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always @(posedge echo_sclk or posedge reset) begin
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if (reset) begin
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data_shift_p <= 0;
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end else begin
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data_shift_p <= {data_shift_p, data_in[i]};
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end
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end
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// DDR output logic - only the first 16 bits are forwarded
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for (j=0; j<DATA_WIDTH/2; j=j+1) begin
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assign m_axis_data[DATA_WIDTH*i+(j*2)+:2] = {data_shift_p[j], data_shift_n[j]};
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end
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end /* for loop */
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end else begin // Single Data Rate mode
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for (i=0; i<NUM_OF_LANES; i=i+1) begin
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reg [DATA_WIDTH-1:0] data_shift_n;
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// shift register for positive edge
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always @(negedge echo_sclk or posedge reset) begin
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if (reset) begin
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data_shift_n <= 0;
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end else begin
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data_shift_n <= {data_shift_n, data_in[i]};
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end
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end
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// SDR output logic
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assign m_axis_data[DATA_WIDTH*i+:DATA_WIDTH] = data_shift_n;
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end /* for loop */
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end
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endgenerate
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endmodule
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