276 lines
8.9 KiB
Verilog
276 lines
8.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad4858_channel #(
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parameter CHANNEL_ID = 0,
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parameter ACTIVE_LANE = 8'b11111111, // for cmos if
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parameter USERPORTS_DISABLE = 0,
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parameter DATAFORMAT_DISABLE = 0
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) (
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// adc interface
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input adc_clk,
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input adc_rst,
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input adc_ch_valid_in,
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input [31:0] adc_ch_data_in,
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input if_crc_err,
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// dma interface
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output adc_enable,
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output reg adc_valid,
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output reg [31:0] adc_data,
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// error monitoring
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output reg adc_or,
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output reg [ 6:0] adc_status_header,
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output up_adc_pn_err,
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output up_adc_pn_oos,
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output up_adc_or,
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// format
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input [ 1:0] packet_format,
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input oversampling_en,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack
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);
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// internal registers
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reg adc_pn_err;
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reg adc_valid_f1;
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reg [23:0] adc_data_f1;
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reg [31:0] pattern;
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reg [31:0] adc_raw_data;
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reg [31:0] read_channel_data;
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reg [31:0] expected_package_pattern;
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// internal signals
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wire to_be_checked;
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wire adc_dfmt_se_s;
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wire adc_dfmt_type_s;
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wire adc_dfmt_enable_s;
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wire adc_pn_err_s;
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wire adc_valid_f2;
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wire [31:0] adc_data_f2;
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wire adc_valid_f2_ovs;
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wire [31:0] adc_data_f2_ovs;
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wire [31:0] expected_pattern;
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wire [31:0] expected_package_pattern_s;
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// expected pattern
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assign expected_pattern = {CHANNEL_ID[3:0], 28'hace3c2a};
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assign expected_package_pattern_s = packet_format == 2'd0 ? expected_pattern >> 12:
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packet_format == 2'd1 ? expected_pattern >> 8:
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packet_format == 2'd2 ? expected_pattern : expected_pattern;
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// the pattern check result is masked out for unused lanes(cmos)
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assign to_be_checked = ACTIVE_LANE[CHANNEL_ID[3:0]] ? 1'b1 : 1'b0;
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always @(posedge adc_clk) begin
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expected_package_pattern <= expected_package_pattern_s;
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if (expected_package_pattern == pattern) begin
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adc_pn_err <= 1'b0;
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end else begin
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adc_pn_err <= to_be_checked;
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end
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end
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// AD4858 is a 20 bit resolution ADC, when oversampling is enabled the data
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// resolutions growes to 24
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always @(posedge adc_clk) begin
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adc_valid_f1 <= adc_ch_valid_in;
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case ({packet_format,oversampling_en})
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3'h0,3'h1: begin // packet format 20 - oversampling on/off
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adc_raw_data <= {12'd0,adc_ch_data_in[19:0]};
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adc_data_f1 <= {4'd0, adc_ch_data_in[19:0]};
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adc_or <= 1'b0;
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adc_status_header <= 7'd0;
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pattern <= {12'd0, adc_ch_data_in[19:0]};
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end
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3'h2: begin // packet format 24 - oversampling off
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adc_raw_data <= {12'd0,adc_ch_data_in[23:4]};
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adc_data_f1 <= {4'd0, adc_ch_data_in[23:4]};
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adc_or <= adc_ch_data_in[3];
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adc_status_header <= {adc_ch_data_in[2:0], 4'd0};
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pattern <= {8'd0, adc_ch_data_in[23:0]};
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end
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3'h3: begin // packet format 24 - oversampling on
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adc_raw_data <= {8'd0,adc_ch_data_in[23:0]};
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adc_data_f1 <= adc_ch_data_in[23:0];
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adc_or <= 3'd0;
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adc_status_header <= 7'd0;
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pattern <= {8'd0, adc_ch_data_in[23:0]};
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end
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3'h4,3'h6: begin // packet format 32 - oversampling off
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adc_raw_data <= {12'd0, adc_ch_data_in[31:12]};
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adc_data_f1 <= {4'd0, adc_ch_data_in[31:12]};
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adc_or <= adc_ch_data_in[11];
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adc_status_header <= adc_ch_data_in[10:4];
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pattern <= adc_ch_data_in;
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end
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3'h5,3'h7: begin // packet format 32 - oversampling on
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adc_raw_data <= {8'd0, adc_ch_data_in[31:8]};
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adc_data_f1 <= adc_ch_data_in[31:8];
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adc_or <= adc_ch_data_in[7];
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adc_status_header <= adc_ch_data_in[6:0];
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pattern <= adc_ch_data_in;
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end
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endcase
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end
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ad_datafmt #(
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.DATA_WIDTH (20),
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.BITS_PER_SAMPLE (32),
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.DISABLE (DATAFORMAT_DISABLE)
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) i_ad_datafmt (
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.clk (adc_clk),
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.valid (adc_valid_f1),
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.data (adc_data_f1[19:0]),
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.valid_out (adc_valid_f2),
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.data_out (adc_data_f2),
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.dfmt_enable (adc_dfmt_enable_s),
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.dfmt_type (adc_dfmt_type_s),
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.dfmt_se (adc_dfmt_se_s));
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ad_datafmt #(
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.DATA_WIDTH (24),
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.BITS_PER_SAMPLE (32),
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.DISABLE (DATAFORMAT_DISABLE)
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) i_ad_datafmt_oversampling (
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.clk (adc_clk),
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.valid (adc_valid_f1),
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.data (adc_data_f1),
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.valid_out (adc_valid_f2_ovs),
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.data_out (adc_data_f2_ovs),
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.dfmt_enable (adc_dfmt_enable_s),
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.dfmt_type (adc_dfmt_type_s),
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.dfmt_se (adc_dfmt_se_s));
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always @(posedge adc_clk) begin
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adc_data <= (packet_format != 'd0 && oversampling_en) ? adc_data_f2_ovs : adc_data_f2;
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adc_valid <= (packet_format != 'd0 && oversampling_en) ? adc_valid_f2_ovs : adc_valid_f2;
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end
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always @(posedge adc_clk) begin
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if (adc_valid_f1) begin
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read_channel_data <= adc_raw_data;
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end else begin
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read_channel_data <= read_channel_data;
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end
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end
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// adc channel regmap
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up_adc_channel #(
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.CHANNEL_ID (CHANNEL_ID),
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.USERPORTS_DISABLE (USERPORTS_DISABLE),
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.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
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.DCFILTER_DISABLE (1'b1),
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.IQCORRECTION_DISABLE (1'b1)
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) i_up_adc_channel (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_enable (adc_enable),
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.adc_iqcor_enb (),
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.adc_dcfilt_enb (),
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.adc_dfmt_se (adc_dfmt_se_s),
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.adc_dfmt_type (adc_dfmt_type_s),
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.adc_dfmt_enable (adc_dfmt_enable_s),
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.adc_dcfilt_offset (),
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.adc_dcfilt_coeff (),
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.adc_iqcor_coeff_1 (),
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.adc_iqcor_coeff_2 (),
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.adc_pnseq_sel (),
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.adc_data_sel (),
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.adc_pn_err (adc_pn_err),
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.adc_pn_oos (1'b0),
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.adc_or (1'b0),
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.adc_read_data (read_channel_data),
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.adc_status_header ({1'b1, adc_status_header}),
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.adc_crc_err (if_crc_err),
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.up_adc_crc_err (),
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.up_adc_pn_err (up_adc_pn_err),
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.up_adc_pn_oos (up_adc_pn_oos),
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.up_adc_or (up_adc_or),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_decimation_m (),
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.up_usr_decimation_n (),
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.adc_usr_datatype_be (1'b0),
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.adc_usr_datatype_signed (1'b1),
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.adc_usr_datatype_shift (8'd0),
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.adc_usr_datatype_total_bits (8'd32),
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.adc_usr_datatype_bits (8'd20),
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.adc_usr_decimation_m (16'd1),
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.adc_usr_decimation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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