337 lines
10 KiB
Verilog
337 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_sg #(
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parameter DMA_AXI_ADDR_WIDTH = 32,
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parameter DMA_DATA_WIDTH = 64,
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parameter DMA_LENGTH_WIDTH = 24,
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parameter AXI_LENGTH_WIDTH = 8,
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parameter BYTES_PER_BEAT_WIDTH_DEST = 3,
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parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
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parameter BYTES_PER_BEAT_WIDTH_SG = 3,
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parameter ASYNC_CLK_REQ_SG = 1
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) (
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input req_clk,
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input req_resetn,
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input req_enable,
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output sg_clk,
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input sg_resetn,
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output sg_ext_resetn,
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input sg_enable,
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output sg_enabled,
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input req_in_valid,
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output req_in_ready,
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output req_out_valid,
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input req_out_ready,
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output resp_out_eot,
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input resp_in_valid,
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input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] req_desc_address,
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output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] out_dest_address,
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output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] out_src_address,
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output [DMA_LENGTH_WIDTH-1:0] out_x_length,
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output [DMA_LENGTH_WIDTH-1:0] out_y_length,
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output [DMA_LENGTH_WIDTH-1:0] out_dest_stride,
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output [DMA_LENGTH_WIDTH-1:0] out_src_stride,
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output [31:0] resp_out_id,
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// Master AXI interface
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input m_axi_aclk,
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input m_axi_aresetn,
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// Read address
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input m_axi_arready,
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output m_axi_arvalid,
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output [DMA_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output [AXI_LENGTH_WIDTH-1:0] m_axi_arlen,
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output [ 2:0] m_axi_arsize,
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output [ 1:0] m_axi_arburst,
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output [ 2:0] m_axi_arprot,
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output [ 3:0] m_axi_arcache,
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// Read data and response
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input [DMA_DATA_WIDTH-1:0] m_axi_rdata,
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input m_axi_rlast,
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output m_axi_rready,
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input m_axi_rvalid,
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input [ 1:0] m_axi_rresp
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);
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localparam STATE_IDLE = 0;
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localparam STATE_SEND_ADDR = 1;
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localparam STATE_RECV_DESC = 2;
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localparam STATE_DESC_READY = 3;
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localparam MASK_LAST_HWDESC = 1 << 0;
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localparam MASK_EOT_IRQ = 1 << 1;
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localparam DMA_ADDRESS_WIDTH_DEST = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;
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localparam DMA_ADDRESS_WIDTH_SRC = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;
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localparam DMA_ADDRESS_WIDTH_SG = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_SG;
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localparam DMA_DESCRIPTOR_WIDTH = DMA_ADDRESS_WIDTH_DEST + DMA_ADDRESS_WIDTH_SRC + 4*DMA_LENGTH_WIDTH;
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wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] first_desc_address;
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reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dest_addr;
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reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_addr;
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reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] next_desc_addr;
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reg [DMA_LENGTH_WIDTH-1:0] x_length;
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reg [DMA_LENGTH_WIDTH-1:0] y_length;
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reg [DMA_LENGTH_WIDTH-1:0] dest_stride;
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reg [DMA_LENGTH_WIDTH-1:0] src_stride;
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reg [1:0] hwdesc_state;
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reg [2:0] hwdesc_counter;
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reg [1:0] hwdesc_flags;
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reg [31:0] hwdesc_id;
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wire sg_in_valid;
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wire sg_in_ready;
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wire sg_out_valid;
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wire sg_out_ready;
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wire fetch_valid;
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wire fetch_ready;
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wire fifo_in_valid;
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wire fifo_in_ready;
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wire fifo_out_valid;
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wire fifo_out_ready;
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wire [32:0] fifo_in_data;
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wire [32:0] fifo_out_data;
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assign sg_clk = m_axi_aclk;
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assign sg_ext_resetn = m_axi_aresetn;
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assign sg_enabled = sg_enable | ~sg_in_ready;
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assign sg_in_ready = hwdesc_state == STATE_IDLE;
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assign fetch_valid = hwdesc_state == STATE_DESC_READY;
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assign m_axi_arvalid = hwdesc_state == STATE_SEND_ADDR;
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assign m_axi_rready = hwdesc_state == STATE_RECV_DESC;
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assign m_axi_arsize = 3'h3;
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assign m_axi_arburst = 2'h1;
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assign m_axi_arprot = 3'h0;
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assign m_axi_arcache = 4'h3;
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assign m_axi_arlen = 'h5;
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assign m_axi_araddr = {next_desc_addr, {BYTES_PER_BEAT_WIDTH_SG{1'b0}}};
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util_axis_fifo #(
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.DATA_WIDTH(DMA_ADDRESS_WIDTH_SG),
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.ADDRESS_WIDTH(0),
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.ASYNC_CLK(ASYNC_CLK_REQ_SG)
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) i_sg_addr_fifo (
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.s_axis_aclk(req_clk),
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.s_axis_aresetn(req_resetn),
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.s_axis_valid(req_in_valid),
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.s_axis_ready(req_in_ready),
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.s_axis_full(),
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.s_axis_data(req_desc_address),
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.s_axis_room(),
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.m_axis_aclk(sg_clk),
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.m_axis_aresetn(sg_resetn),
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.m_axis_valid(sg_in_valid),
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.m_axis_ready(sg_in_ready),
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.m_axis_data(first_desc_address),
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.m_axis_level(),
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.m_axis_empty());
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always @(posedge sg_clk) begin
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if (sg_resetn == 1'b0) begin
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hwdesc_counter <= 'h0;
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end else if (m_axi_rvalid) begin
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hwdesc_counter <= hwdesc_counter + 1'b1;
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end else if (hwdesc_state == STATE_DESC_READY) begin
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hwdesc_counter <= 'h0;
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end
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end
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// Read the descriptor data
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always @(posedge sg_clk) begin
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if (sg_resetn == 1'b0) begin
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hwdesc_flags <= 'h00;
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hwdesc_id <= 'h00;
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dest_addr <= 'h00;
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src_addr <= 'h00;
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next_desc_addr <= 'h00;
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y_length <= 'h00;
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x_length <= 'h00;
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src_stride <= 'h00;
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dest_stride <= 'h00;
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end else begin
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if (sg_in_valid && sg_in_ready) begin
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next_desc_addr <= first_desc_address;
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end
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if (m_axi_rvalid) begin
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case (hwdesc_counter)
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0: begin
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hwdesc_id <= m_axi_rdata[63:32];
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hwdesc_flags <= m_axi_rdata[1:0];
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end
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1: dest_addr <= m_axi_rdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
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2: src_addr <= m_axi_rdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
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3: next_desc_addr <= m_axi_rdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG];
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4: begin
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x_length <= m_axi_rdata[63:32];
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y_length <= m_axi_rdata[31:0];
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end
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5: begin
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dest_stride <= m_axi_rdata[63:32];
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src_stride <= m_axi_rdata[31:0];
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end
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endcase
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end
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end
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end
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// Descriptor FSM
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always @(posedge sg_clk) begin
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if (sg_resetn == 1'b0) begin
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hwdesc_state <= STATE_IDLE;
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end else begin
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case (hwdesc_state)
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STATE_IDLE: begin
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if (sg_in_valid == 1'b1 && sg_enable == 1'b1) begin
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hwdesc_state <= STATE_SEND_ADDR;
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end
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end
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STATE_SEND_ADDR: begin
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if (m_axi_arready) begin
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hwdesc_state <= STATE_RECV_DESC;
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end
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end
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STATE_RECV_DESC: begin
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if (m_axi_rvalid == 1'b1 && m_axi_rlast == 1'b1) begin
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hwdesc_state <= STATE_DESC_READY;
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end
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end
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STATE_DESC_READY: begin
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if (sg_enable == 1'b0) begin
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hwdesc_state <= STATE_IDLE;
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end else if (fetch_ready == 1'b1) begin
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if (hwdesc_flags & MASK_LAST_HWDESC) begin
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hwdesc_state <= STATE_IDLE;
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end else begin
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hwdesc_state <= STATE_SEND_ADDR;
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end
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end
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end
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endcase
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end
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end
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util_axis_fifo #(
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.DATA_WIDTH(DMA_DESCRIPTOR_WIDTH),
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.ADDRESS_WIDTH(0),
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.ASYNC_CLK(ASYNC_CLK_REQ_SG)
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) i_sg_desc_fifo (
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.s_axis_aclk(sg_clk),
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.s_axis_aresetn(sg_resetn),
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.s_axis_valid(sg_out_valid),
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.s_axis_ready(sg_out_ready),
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.s_axis_full(),
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.s_axis_data({
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dest_addr,
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src_addr,
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x_length,
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y_length,
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dest_stride,
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src_stride}),
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.s_axis_room(),
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.m_axis_aclk(req_clk),
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.m_axis_aresetn(req_resetn),
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.m_axis_valid(req_out_valid),
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.m_axis_ready(req_out_ready),
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.m_axis_data({
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out_dest_address,
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out_src_address,
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out_x_length,
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out_y_length,
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out_dest_stride,
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out_src_stride}),
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.m_axis_level(),
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.m_axis_empty());
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splitter #(
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.NUM_M(2)
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) i_req_splitter (
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.clk(sg_clk),
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.resetn(sg_resetn),
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.s_valid(fetch_valid),
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.s_ready(fetch_ready),
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.m_valid({
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sg_out_valid,
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fifo_in_valid}),
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.m_ready({
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sg_out_ready,
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fifo_in_ready}));
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assign fifo_in_data = {hwdesc_flags & MASK_EOT_IRQ ? 1'b1 : 1'b0, hwdesc_id};
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assign fifo_out_ready = resp_in_valid;
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assign resp_out_eot = fifo_out_data[32];
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assign resp_out_id = fifo_out_data[31:0];
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// Save the descriptor IDs and the eot descriptor flag in an async fifo
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// Extract them one by one when the destination responds with an eot
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util_axis_fifo #(
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.DATA_WIDTH(33),
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.ADDRESS_WIDTH(2),
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.ASYNC_CLK(ASYNC_CLK_REQ_SG)
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) i_fifo (
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.s_axis_aclk(sg_clk),
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.s_axis_aresetn(sg_resetn),
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.s_axis_valid(fifo_in_valid),
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.s_axis_ready(fifo_in_ready),
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.s_axis_data(fifo_in_data),
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.m_axis_aclk(req_clk),
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.m_axis_aresetn(req_resetn),
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.m_axis_valid(fifo_out_valid),
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.m_axis_ready(fifo_out_ready),
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.m_axis_data(fifo_out_data));
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endmodule
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