49 lines
1.7 KiB
Tcl
49 lines
1.7 KiB
Tcl
###############################################################################
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## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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package require qsys 14.0
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source ../../scripts/adi_env.tcl
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source ../scripts/adi_ip_intel.tcl
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ad_ip_create util_dacfifo {UTIL DAC FIFO Interface}
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ad_ip_files util_dacfifo [list\
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$ad_hdl_dir/library/common/ad_mem.v \
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$ad_hdl_dir/library/common/ad_mem_asym.v \
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$ad_hdl_dir/library/common/ad_b2g.v \
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$ad_hdl_dir/library/common/ad_g2b.v \
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util_dacfifo.v \
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util_dacfifo_bypass.v \
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util_dacfifo_constr.sdc]
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter ADDRESS_WIDTH INTEGER 6
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ad_ip_parameter DATA_WIDTH INTEGER 128
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# interfaces
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ad_interface clock dma_clk input 1 clk
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ad_interface reset dma_rst input 1 if_dma_clk
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ad_interface signal dma_xfer_req input 1 xfer_req
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add_interface s_axis axi4stream end
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set_interface_property s_axis associatedClock if_dma_clk
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set_interface_property s_axis associatedReset if_dma_rst
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add_interface_port s_axis dma_valid tvalid Input 1
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add_interface_port s_axis dma_xfer_last tlast Input 1
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add_interface_port s_axis dma_ready tready Output 1
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add_interface_port s_axis dma_data tdata Input DATA_WIDTH
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ad_interface clock dac_clk input 1
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ad_interface reset dac_rst input 1 if_dac_clk
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ad_interface signal dac_valid input 1 valid
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ad_interface signal dac_data output DATA_WIDTH data
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ad_interface signal dac_xfer_out output 1 xfer_req
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ad_interface signal dac_dunf output 1 unf
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ad_interface signal bypass input 1 bypass
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