57 lines
2.1 KiB
Tcl
57 lines
2.1 KiB
Tcl
###############################################################################
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## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# unused
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ad_connect sys_ps7/ENET1_GMII_RX_CLK GND
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ad_connect sys_ps7/ENET1_GMII_TX_CLK GND
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# GPS-UART
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set_property CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_USE_DMA0 1 [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7]
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# enable PPS receiver
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ad_ip_parameter axi_ad9361 CONFIG.PPS_RECEIVER_ENABLE 1
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# i2s
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create_bd_port -dir O -type clk i2s_mclk
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create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
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ad_ip_instance clk_wiz sys_audio_clkgen
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ad_ip_parameter sys_audio_clkgen CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 12.288
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ad_ip_parameter sys_audio_clkgen CONFIG.USE_LOCKED false
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ad_ip_parameter sys_audio_clkgen CONFIG.USE_RESET true
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ad_ip_parameter sys_audio_clkgen CONFIG.RESET_TYPE ACTIVE_LOW
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ad_ip_parameter sys_audio_clkgen CONFIG.USE_PHASE_ALIGNMENT false
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ad_ip_parameter sys_audio_clkgen CONFIG.PRIM_SOURCE No_buffer
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ad_ip_instance axi_i2s_adi axi_i2s_adi
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ad_ip_parameter axi_i2s_adi CONFIG.DMA_TYPE 1
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ad_ip_parameter axi_i2s_adi CONFIG.S_AXI_ADDRESS_WIDTH 16
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ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
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ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
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ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
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ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
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ad_connect sys_ps7/DMA0_REQ axi_i2s_adi/DMA_REQ_TX
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ad_connect sys_ps7/DMA0_ACK axi_i2s_adi/DMA_ACK_TX
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ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_RX
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ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_RX
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ad_connect sys_audio_clkgen/clk_out1 i2s_mclk
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ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
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ad_connect i2s axi_i2s_adi/I2S
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ad_cpu_interconnect 0x77600000 axi_i2s_adi
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