181 lines
8.8 KiB
Tcl
181 lines
8.8 KiB
Tcl
###############################################################################
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## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# receive dma
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add_instance axi_dmac_0 axi_dmac
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set_instance_parameter_value axi_dmac_0 {DMA_TYPE_SRC} {1}
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set_instance_parameter_value axi_dmac_0 {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
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set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {128}
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set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128}
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# axi_spi_engine
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add_instance axi_spi_engine_0 axi_spi_engine
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set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
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set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32}
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set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0}
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set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {4}
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set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1}
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# spi_engine_execution
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add_instance spi_engine_execution_0 spi_engine_execution
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set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
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set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {4}
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set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
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# spi_engine_interconnect
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add_instance spi_engine_interconnect_0 spi_engine_interconnect
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set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
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set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {4}
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# spi_engine_offload
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add_instance spi_engine_offload_0 spi_engine_offload
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set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1}
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set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
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set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32}
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set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {4}
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# axi pwm gen
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add_instance odr_generator axi_pwm_gen
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set_instance_parameter_value odr_generator {N_PWMS} {2}
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set_instance_parameter_value odr_generator {PULSE_0_PERIOD} {85}
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set_instance_parameter_value odr_generator {PULSE_0_WIDTH} {1}
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set_instance_parameter_value odr_generator {PULSE_1_PERIOD} {85}
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set_instance_parameter_value odr_generator {PULSE_1_WIDTH} {13}
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set_instance_parameter_value odr_generator {PULSE_1_OFFSET} {3}
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# spi_clk pll
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add_instance spi_clk_pll altera_pll
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set_instance_parameter_value spi_clk_pll {gui_feedback_clock} {Global Clock}
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set_instance_parameter_value spi_clk_pll {gui_operation_mode} {direct}
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set_instance_parameter_value spi_clk_pll {gui_number_of_clocks} {1}
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set_instance_parameter_value spi_clk_pll {gui_output_clock_frequency0} {96}
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set_instance_parameter_value spi_clk_pll {gui_phase_shift0} {0}
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set_instance_parameter_value spi_clk_pll {gui_phase_shift1} {0}
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set_instance_parameter_value spi_clk_pll {gui_phase_shift_deg0} {0.0}
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set_instance_parameter_value spi_clk_pll {gui_phase_shift_deg1} {0.0}
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set_instance_parameter_value spi_clk_pll {gui_phout_division} {1}
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set_instance_parameter_value spi_clk_pll {gui_pll_auto_reset} {Off}
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set_instance_parameter_value spi_clk_pll {gui_pll_bandwidth_preset} {Auto}
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set_instance_parameter_value spi_clk_pll {gui_pll_mode} {Fractional-N PLL}
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set_instance_parameter_value spi_clk_pll {gui_ps_units0} {ps}
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set_instance_parameter_value spi_clk_pll {gui_refclk_switch} {0}
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set_instance_parameter_value spi_clk_pll {gui_reference_clock_frequency} {50.0}
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set_instance_parameter_value spi_clk_pll {gui_switchover_delay} {0}
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set_instance_parameter_value spi_clk_pll {gui_en_reconf} {1}
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add_instance spi_clk_pll_reconfig altera_pll_reconfig
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set_instance_parameter_value spi_clk_pll_reconfig {ENABLE_BYTEENABLE} {0}
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set_instance_parameter_value spi_clk_pll_reconfig {ENABLE_MIF} {0}
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set_instance_parameter_value spi_clk_pll_reconfig {MIF_FILE_NAME} {}
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add_connection spi_clk_pll.reconfig_from_pll spi_clk_pll_reconfig.reconfig_from_pll
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set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll endPort {}
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set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll endPortLSB {0}
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set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll startPort {}
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set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll startPortLSB {0}
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set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll width {0}
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add_connection spi_clk_pll.reconfig_to_pll spi_clk_pll_reconfig.reconfig_to_pll
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set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll endPort {}
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set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll endPortLSB {0}
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set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPort {}
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set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0}
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set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0}
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# exported interface
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add_interface cn0561_spi_sclk clock source
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add_interface cn0561_spi_cs conduit end
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add_interface cn0561_spi_sdi conduit end
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add_interface cn0561_spi_sdo conduit end
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add_interface ad4134_odr conduit end
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set_interface_property cn0561_spi_cs EXPORT_OF spi_engine_execution_0.if_cs
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set_interface_property cn0561_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk
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set_interface_property cn0561_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi
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set_interface_property cn0561_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo
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set_interface_property ad4134_odr EXPORT_OF odr_generator.if_pwm_1
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# clocks
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add_connection sys_clk.clk spi_clk_pll.refclk
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add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
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add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
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add_connection sys_clk.clk axi_dmac_0.s_axi_clock
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add_connection sys_clk.clk odr_generator.s_axi_clock
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add_connection spi_clk_pll.outclk0 odr_generator.if_ext_clk
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add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk
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add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk
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add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk
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add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk
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add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk
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add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk
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add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
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# resets
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add_connection sys_clk.clk_reset spi_clk_pll.reset
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add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset
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add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
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add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
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add_connection sys_clk.clk_reset odr_generator.s_axi_reset
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add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
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add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
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add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
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add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
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# interfaces
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add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
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add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
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add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
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add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
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add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s0_cmd
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add_connection spi_engine_interconnect_0.s0_sdi axi_spi_engine_0.sdi_data
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add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s0_sdo
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add_connection spi_engine_interconnect_0.s0_sync axi_spi_engine_0.sync
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add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s1_cmd
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add_connection spi_engine_interconnect_0.s1_sdi spi_engine_offload_0.sdi_data
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add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s1_sdo
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add_connection spi_engine_interconnect_0.s1_sync spi_engine_offload_0.sync
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add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd
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add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo
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add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable
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add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled
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add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
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add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync
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add_connection spi_engine_offload_0.if_trigger odr_generator.if_pwm_0
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add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
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# cpu interconnects
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ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
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ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
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ad_cpu_interconnect 0x00040000 odr_generator.s_axi
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# dma interconnect
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ad_dma_interconnect axi_dmac_0.m_dest_axi
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#interrupts
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ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
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ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
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