kylex 365933542d scripts/adi_board.tcl: use axi_interconnect for HP ports on Zynq-7000 family ... Commit 5db7574 switched ad_cpu_interconnect from SmartConnect to AXI Interconnect for Zynq-7000 family SoC. This commit does the same for ad_mem_hpx_interconnect. Signed-off-by: Alexander Vickberg <wickbergster@gmail.com> Signed-off-by: Jorge Marques <jorge.marques@analog.com>		2023-10-30 09:48:32 -03:00
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adi_board.tcl	scripts/adi_board.tcl: use axi_interconnect for HP ports on Zynq-7000 family	2023-10-30 09:48:32 -03:00
adi_fmc_constr_generator.tcl	scripts/adi_fmc_constr_generator: Fix intel constr generation	2023-08-14 18:05:02 +03:00
adi_intel_msg.tcl	Add copyright and license to .tcl, .ttcl files	2023-07-25 15:22:26 +03:00
adi_make.tcl	Add copyright and license to .tcl, .ttcl files	2023-07-25 15:22:26 +03:00
adi_make_boot_bin.tcl	Add copyright and license to .tcl, .ttcl files	2023-07-25 15:22:26 +03:00
adi_pd.tcl	Add copyright and license to .tcl, .ttcl files	2023-07-25 15:22:26 +03:00
adi_project_intel.tcl	Add copyright and license to .tcl, .ttcl files	2023-07-25 15:22:26 +03:00
adi_project_xilinx.tcl	scripts/adi_board.tcl: use axi_interconnect for HP ports on Zynq-7000 family	2023-10-30 09:48:32 -03:00
adi_tquest.tcl	Add copyright and license to .tcl, .ttcl files	2023-07-25 15:22:26 +03:00
adi_xilinx_msg.tcl	Add copyright and license to .tcl, .ttcl files	2023-07-25 15:22:26 +03:00
gtwiz_parser.pl	Add copyright & license to .sh, .yml, .pl files. Edit Makefile for KV260	2023-07-11 18:39:55 +03:00
gtwizard_generator.tcl	Add copyright and license to .tcl, .ttcl files	2023-07-25 15:22:26 +03:00
project-intel.mk	projects/scripts/project-intel.mk: change 'system_top.v' to '$(wildcard system_top*.v)' (#1169)	2023-09-07 15:52:04 +08:00
project-toplevel.mk	Make system: Be explicit in license that cover the make/build system	2021-09-16 16:50:53 +03:00
project-xilinx.mk	project-xilinx: Update the generic dependency list	2023-09-07 10:44:10 +03:00