pluto_hdl_adi/projects/common
Laszlo Nagy b7d48b8c74 common/vcu118: Balance clocks
Minimize skew on synchronous CDC timing paths between clocks originating
from the same MMCM source. (sys_mem_clk and sys_cpu_clk)
This is required mostly by the smart interconnect.
The CLOCK_DELAY_GROUP property must be applied directly to the output net of BUFGs.
2019-09-16 10:00:14 +03:00
..
a10gx a10gx: Optimise the base design 2019-06-04 11:28:37 +03:00
a10soc whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
ac701 system_id: deployed ip 2019-08-06 16:53:11 +03:00
c5soc Remove executable flag from non-executable files 2017-07-28 17:56:07 +02:00
de10 DE10: Initial commit 2018-04-11 15:09:54 +03:00
intel adi_env: Update system level environment variable definition 2019-07-22 11:00:45 +03:00
kc705 system_id: deployed ip 2019-08-06 16:53:11 +03:00
kcu105 system_id: deployed ip 2019-08-06 16:53:11 +03:00
microzed system_id: deployed ip 2019-08-06 16:53:11 +03:00
vc707 system_id: deployed ip 2019-08-06 16:53:11 +03:00
vcu118 common/vcu118: Balance clocks 2019-09-16 10:00:14 +03:00
xilinx Add generic fir filters processes for RF projects 2019-08-20 16:24:47 +03:00
zc702 zynq:all: fix SPI clock constraint 2019-08-09 16:39:56 +03:00
zc706 zynq:all: fix SPI clock constraint 2019-08-09 16:39:56 +03:00
zcu102 zynq:all: fix SPI clock constraint 2019-08-09 16:39:56 +03:00
zed zynq:all: fix SPI clock constraint 2019-08-09 16:39:56 +03:00