63 lines
2.4 KiB
Verilog
63 lines
2.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns / 1ps
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module delay
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//----------- Parameters Declarations -------------------------------------------
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#(
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parameter DELAY = 128
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)
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//----------- Ports Declarations -----------------------------------------------
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(
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input clk_i,
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input rst_n_i,
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input sig_i,
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output reg sig_o
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);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [DELAY-1:0] shift_reg;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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always @(posedge clk_i)
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begin
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if(rst_n_i == 0)
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begin
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shift_reg <= 0;
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sig_o <= 0;
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end
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else
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begin
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shift_reg <= {shift_reg[DELAY-2:0], sig_i};
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sig_o <= shift_reg[DELAY-1];
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end
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end
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endmodule
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