240 lines
6.9 KiB
Verilog
240 lines
6.9 KiB
Verilog
// ***************************************************************************
|
|
// ***************************************************************************
|
|
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
|
//
|
|
// In this HDL repository, there are many different and unique modules, consisting
|
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
|
// developed independently, and may be accompanied by separate and unique license
|
|
// terms.
|
|
//
|
|
// The user should read each of these license terms, and understand the
|
|
// freedoms and responsabilities that he or she has by using this source/core.
|
|
//
|
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
|
// A PARTICULAR PURPOSE.
|
|
//
|
|
// Redistribution and use of source or resulting binaries, with or without modification
|
|
// of this file, are permitted under one of the following two license terms:
|
|
//
|
|
// 1. The GNU General Public License version 2 as published by the
|
|
// Free Software Foundation, which can be found in the top level directory
|
|
// of this repository (LICENSE_GPL2), and also online at:
|
|
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
|
//
|
|
// OR
|
|
//
|
|
// 2. An ADI specific BSD license, which can be found in the top level directory
|
|
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
|
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
|
// This will allow to generate bit files and not release the source code,
|
|
// as long as it attaches to an ADI device.
|
|
//
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|
|
|
|
`timescale 1ns/100ps
|
|
|
|
module system_top (
|
|
|
|
inout [14:0] ddr_addr,
|
|
inout [ 2:0] ddr_ba,
|
|
inout ddr_cas_n,
|
|
inout ddr_ck_n,
|
|
inout ddr_ck_p,
|
|
inout ddr_cke,
|
|
inout ddr_cs_n,
|
|
inout [ 3:0] ddr_dm,
|
|
inout [31:0] ddr_dq,
|
|
inout [ 3:0] ddr_dqs_n,
|
|
inout [ 3:0] ddr_dqs_p,
|
|
inout ddr_odt,
|
|
inout ddr_ras_n,
|
|
inout ddr_reset_n,
|
|
inout ddr_we_n,
|
|
|
|
inout fixed_io_ddr_vrn,
|
|
inout fixed_io_ddr_vrp,
|
|
inout [53:0] fixed_io_mio,
|
|
inout fixed_io_ps_clk,
|
|
inout fixed_io_ps_porb,
|
|
inout fixed_io_ps_srstb,
|
|
|
|
inout iic_scl,
|
|
inout iic_sda,
|
|
|
|
input rx_clk_in_p,
|
|
input rx_clk_in_n,
|
|
input rx_frame_in_p,
|
|
input rx_frame_in_n,
|
|
input [ 5:0] rx_data_in_p,
|
|
input [ 5:0] rx_data_in_n,
|
|
output tx_clk_out_p,
|
|
output tx_clk_out_n,
|
|
output tx_frame_out_p,
|
|
output tx_frame_out_n,
|
|
output [ 5:0] tx_data_out_p,
|
|
output [ 5:0] tx_data_out_n,
|
|
|
|
output enable,
|
|
output txnrx,
|
|
input clkout_in,
|
|
|
|
inout gpio_clksel,
|
|
inout gpio_resetb,
|
|
inout gpio_sync,
|
|
inout gpio_en_agc,
|
|
inout [ 3:0] gpio_ctl,
|
|
inout [ 7:0] gpio_status,
|
|
|
|
input usb_fx3_uart_tx,
|
|
output usb_fx3_uart_rx,
|
|
|
|
input [ 7:0] fifo_rdy,
|
|
|
|
inout [31:0] data,
|
|
output [ 4:0] addr,
|
|
output pclk,
|
|
output slcs_n,
|
|
output slrd_n,
|
|
output sloe_n,
|
|
output slwr_n,
|
|
output pktend_n,
|
|
output epswitch_n,
|
|
|
|
input flag_a,
|
|
input flag_b,
|
|
|
|
output reset_n,
|
|
|
|
output [ 2:0] pmode,
|
|
|
|
output spi_csn,
|
|
output spi_clk,
|
|
output spi_mosi,
|
|
input spi_miso);
|
|
|
|
// internal signals
|
|
|
|
wire [63:0] gpio_i;
|
|
wire [63:0] gpio_o;
|
|
wire [63:0] gpio_t;
|
|
|
|
// assignments
|
|
|
|
assign pmode = 3'b111;
|
|
assign addr[4:2] = 3'b000;
|
|
|
|
assign epswitch_n = 1'b1;
|
|
assign reset_n = 1'b1;
|
|
|
|
// instantiations
|
|
|
|
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
|
|
.dio_t ({gpio_t[51], gpio_t[46:32]}),
|
|
.dio_i ({gpio_o[51], gpio_o[46:32]}),
|
|
.dio_o ({gpio_i[51], gpio_i[46:32]}),
|
|
.dio_p ({ gpio_clksel, // 51:51
|
|
gpio_resetb, // 46:46
|
|
gpio_sync, // 45:45
|
|
gpio_en_agc, // 44:44
|
|
gpio_ctl, // 43:40
|
|
gpio_status})); // 39:32
|
|
|
|
system_wrapper i_system_wrapper (
|
|
.ddr_addr (ddr_addr),
|
|
.ddr_ba (ddr_ba),
|
|
.ddr_cas_n (ddr_cas_n),
|
|
.ddr_ck_n (ddr_ck_n),
|
|
.ddr_ck_p (ddr_ck_p),
|
|
.ddr_cke (ddr_cke),
|
|
.ddr_cs_n (ddr_cs_n),
|
|
.ddr_dm (ddr_dm),
|
|
.ddr_dq (ddr_dq),
|
|
.ddr_dqs_n (ddr_dqs_n),
|
|
.ddr_dqs_p (ddr_dqs_p),
|
|
.ddr_odt (ddr_odt),
|
|
.ddr_ras_n (ddr_ras_n),
|
|
.ddr_reset_n (ddr_reset_n),
|
|
.ddr_we_n (ddr_we_n),
|
|
.enable (enable),
|
|
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
|
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
|
.fixed_io_mio (fixed_io_mio),
|
|
.fixed_io_ps_clk (fixed_io_ps_clk),
|
|
.fixed_io_ps_porb (fixed_io_ps_porb),
|
|
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
|
.gpio_i (gpio_i),
|
|
.gpio_o (gpio_o),
|
|
.gpio_t (gpio_t),
|
|
.iic_main_scl_io (iic_scl),
|
|
.iic_main_sda_io (iic_sda),
|
|
.otg_vbusoc (1'b0),
|
|
.ps_intr_00 (1'b0),
|
|
.ps_intr_01 (1'b0),
|
|
.ps_intr_02 (1'b0),
|
|
.ps_intr_03 (1'b0),
|
|
.ps_intr_04 (1'b0),
|
|
.ps_intr_05 (1'b0),
|
|
.ps_intr_06 (1'b0),
|
|
.ps_intr_07 (1'b0),
|
|
.ps_intr_08 (1'b0),
|
|
.ps_intr_09 (1'b0),
|
|
.ps_intr_15 (1'b0),
|
|
.rx_clk_in_n (rx_clk_in_n),
|
|
.rx_clk_in_p (rx_clk_in_p),
|
|
.rx_data_in_n (rx_data_in_n),
|
|
.rx_data_in_p (rx_data_in_p),
|
|
.rx_frame_in_n (rx_frame_in_n),
|
|
.rx_frame_in_p (rx_frame_in_p),
|
|
.spi0_clk_i (1'b0),
|
|
.spi0_clk_o (spi_clk),
|
|
.spi0_csn_0_o (spi_csn),
|
|
.spi0_csn_1_o (),
|
|
.spi0_csn_2_o (),
|
|
.spi0_csn_i (1'b1),
|
|
.spi0_sdi_i (spi_miso),
|
|
.spi0_sdo_i (1'b0),
|
|
.spi0_sdo_o (spi_mosi),
|
|
.spi1_clk_i (1'b0),
|
|
.spi1_clk_o (),
|
|
.spi1_csn_0_o (),
|
|
.spi1_csn_1_o (),
|
|
.spi1_csn_2_o (),
|
|
.spi1_csn_i (1'b1),
|
|
.spi1_sdi_i (1'b0),
|
|
.spi1_sdo_i (1'b0),
|
|
.spi1_sdo_o (),
|
|
.tdd_sync_i (1'b0),
|
|
.tdd_sync_o (),
|
|
.tdd_sync_t (),
|
|
.tx_clk_out_n (tx_clk_out_n),
|
|
.tx_clk_out_p (tx_clk_out_p),
|
|
.tx_data_out_n (tx_data_out_n),
|
|
.tx_data_out_p (tx_data_out_p),
|
|
.tx_frame_out_n (tx_frame_out_n),
|
|
.tx_frame_out_p (tx_frame_out_p),
|
|
.txnrx (txnrx),
|
|
.up_enable (gpio_o[47]),
|
|
.up_txnrx (gpio_o[48]),
|
|
.usb_fx3_uart_tx(usb_fx3_uart_tx),
|
|
.usb_fx3_uart_rx(usb_fx3_uart_rx),
|
|
.dma_rdy(),
|
|
.dma_wmk(),
|
|
.fifo_rdy(fifo_rdy[3:0]),
|
|
.pclk(pclk),
|
|
.data(data),
|
|
.addr(addr[1:0]),
|
|
.slcs_n(slcs_n),
|
|
.slrd_n(slrd_n),
|
|
.sloe_n(sloe_n),
|
|
.slwr_n(slwr_n),
|
|
// .epswitch_n(epswitch_n),
|
|
.pktend_n(pktend_n)
|
|
);
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|