Istvan Csomortani 19732d89fb plddr3: Fix the adc_dwr pulse width ... The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.		2014-12-09 13:51:00 +02:00
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axi_fifo2s.v	axi_fifo2s: include bus width/clock transfer	2014-11-12 14:43:37 -05:00
axi_fifo2s_adc.v	plddr3: Fix the adc_dwr pulse width	2014-12-09 13:51:00 +02:00
axi_fifo2s_constr.xdc	axi_fifo2s: include bus width/clock transfer	2014-11-12 14:43:40 -05:00
axi_fifo2s_dma.v	axi_fifo2s: buswidth fix	2014-11-12 14:43:46 -05:00
axi_fifo2s_ip.tcl	fifo2s: removed m interface	2014-11-13 15:00:03 -05:00
axi_fifo2s_rd.v	axi_fifo2s: fifo full replaced with ready	2014-11-12 14:43:47 -05:00
axi_fifo2s_wr.v	axi_fifo2s: include bus width/clock transfer	2014-11-12 14:43:44 -05:00