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pluto_hdl_adi/library/altera
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AndreiGrozav 568f2e180f ad_mul.v: Add parameters for A and B input widths 
The out width will be A + B.
This change is backward compatible and it applies to both Altera and Xilinx.
 		2018-07-18 18:19:30 +03:00
..
adi_jesd204 altera: jesd204: Add support for lane polarity inversion 2018-05-02 09:37:23 +02:00
avl_adxcfg Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
avl_adxcvr Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
avl_adxcvr_octet_swap Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
avl_adxphy Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
avl_dacfifo util_dacfifo_bypass: Update comments 2018-06-11 17:26:04 +03:00
axi_adxcvr Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
common ad_mul.v: Add parameters for A and B input widths 2018-07-18 18:19:30 +03:00
jesd204_phy altera: jesd204: Add support for lane polarity inversion 2018-05-02 09:37:23 +02:00