121 lines
4.1 KiB
Verilog
121 lines
4.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This is the LVDS/DDR interface
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`timescale 1ns/100ps
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module axi_ad9250_if (
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// jesd interface
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// rx_clk is (line-rate/40)
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rx_clk,
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rx_data,
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// adc data output
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adc_clk,
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adc_rst,
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adc_data_a,
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adc_data_b,
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adc_or_a,
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adc_or_b,
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adc_status);
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk;
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input [63:0] rx_data;
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// adc data output
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output adc_clk;
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input adc_rst;
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output [27:0] adc_data_a;
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output [27:0] adc_data_b;
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output adc_or_a;
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output adc_or_b;
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output adc_status;
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// internal registers
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reg adc_status = 'd0;
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// internal signals
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wire [15:0] adc_data_a_s1_s;
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wire [15:0] adc_data_a_s0_s;
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wire [15:0] adc_data_b_s1_s;
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wire [15:0] adc_data_b_s0_s;
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// adc clock is the reference clock
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assign adc_clk = rx_clk;
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assign adc_or_a = 1'b0;
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assign adc_or_b = 1'b0;
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// adc channels
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assign adc_data_a = {adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]};
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assign adc_data_b = {adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]};
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// data multiplex
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assign adc_data_a_s1_s = {rx_data[25:24], rx_data[23:16], rx_data[31:26]};
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assign adc_data_a_s0_s = {rx_data[ 9: 8], rx_data[ 7: 0], rx_data[15:10]};
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assign adc_data_b_s1_s = {rx_data[57:56], rx_data[55:48], rx_data[63:58]};
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assign adc_data_b_s0_s = {rx_data[41:40], rx_data[39:32], rx_data[47:42]};
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// status
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always @(posedge rx_clk) begin
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if (adc_rst == 1'b1) begin
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adc_status <= 1'b0;
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end else begin
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adc_status <= 1'b1;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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