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pluto_hdl_adi/library/axi_dmac
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Lars-Peter Clausen 7d643e216a axi_dmac: Limit number of bursts on the source side 
Currently the source side of the DMAC can issue requests for up to
2*FIFO_SIZE-1 bursts even though there is only room for FIFO_SIZE bursts in
the store and forward memory.

This can problematic for memory mapped buses. If the data is not read fast
enough from the DMAC back-pressure will propagate through the whole system
memory subsystem and can cause significant performance penalty or even a
deadlock halting the whole system.

To avoid this make sure that not more that than what fits into the
store-and-forward memory is requested by throttling the request ID based
on how much room is available in the memory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-07-03 13:44:34 +02:00
..
bd axi_dmac: Limit MAX_BYTES_PER_BURST to maximum supported value 2018-04-24 12:49:24 +02:00
tb axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
2d_transfer.v axi_dmac: 2d_transfer: Remove resets from data path 2018-06-05 14:28:40 +02:00
Makefile axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
address_generator.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
axi_dmac.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
axi_dmac_burst_memory.v axi_dmac: Limit number of bursts on the source side 2018-07-03 13:44:34 +02:00
axi_dmac_constr.sdc axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_constr.ttcl axi_dmac: Route destination request ID through the burst memory 2018-07-03 13:44:34 +02:00
axi_dmac_hw.tcl axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_ip.tcl axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_regmap.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
axi_dmac_regmap_request.v axi_dmac: Split register map into separate sub-module 2018-05-03 14:49:06 +02:00
axi_dmac_reset_manager.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
axi_dmac_resize_dest.v axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_resize_src.v axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_transfer.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
axi_register_slice.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
data_mover.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
dest_axi_mm.v axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
dest_axi_stream.v axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
dest_fifo_inf.v axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
inc_id.h axi_dmac: Fix some data width mismatches 2017-08-01 15:22:29 +02:00
request_arb.v axi_dmac: Limit number of bursts on the source side 2018-07-03 13:44:34 +02:00
request_generator.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
resp.h Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00
response_generator.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
response_handler.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
splitter.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
src_axi_mm.v axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
src_axi_stream.v axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
src_fifo_inf.v axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00