233 lines
7.2 KiB
Verilog
233 lines
7.2 KiB
Verilog
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg_dac(
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clk,
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// control ports
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control,
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status,
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// FIFO interface
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src_dac_en,
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src_dac_ddata,
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src_dac_dunf,
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src_dac_dvalid,
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dst_dac_en,
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dst_dac_ddata,
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dst_dac_dunf,
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dst_dac_dvalid
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);
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localparam RP_ID = 8'hA1;
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parameter CHANNEL_ID = 0;
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input clk;
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input [31:0] control;
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output [31:0] status;
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output src_dac_en;
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input [31:0] src_dac_ddata;
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input src_dac_dunf;
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input src_dac_dvalid;
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input dst_dac_en;
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output [31:0] dst_dac_ddata;
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output dst_dac_dunf;
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output dst_dac_dvalid;
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reg dst_dac_dunf = 0;
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reg [31:0] dst_dac_ddata = 0;
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reg dst_dac_dvalid = 0;
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reg src_dac_en = 0;
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reg [31:0] dac_prbs = 32'hA2F19C;
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reg [31:0] status = 0;
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reg [ 2:0] counter = 0;
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reg pattern = 0;
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reg [15:0] sin_tone = 0;
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reg [15:0] cos_tone = 0;
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reg [ 3:0] mode;
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wire [31:0] dac_pattern_s;
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// prbs function
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function [31:0] pn;
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input [31:0] din;
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reg [31:0] dout;
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begin
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dout[31] = din[14] ^ din[13];
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dout[30] = din[13] ^ din[12];
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dout[29] = din[12] ^ din[11];
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dout[28] = din[11] ^ din[10];
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dout[27] = din[10] ^ din[9];
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dout[26] = din[9] ^ din[8];
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dout[25] = din[8] ^ din[7];
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dout[24] = din[7] ^ din[6];
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dout[23] = din[6] ^ din[5];
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dout[22] = din[5] ^ din[4];
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dout[21] = din[4] ^ din[3];
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dout[20] = din[3] ^ din[2];
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dout[19] = din[2] ^ din[1];
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dout[18] = din[1] ^ din[0];
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dout[17] = din[0] ^ din[14] ^ din[13];
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dout[16] = din[14] ^ din[12];
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dout[15] = din[13] ^ din[11];
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dout[14] = din[12] ^ din[10];
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dout[13] = din[11] ^ din[9];
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dout[12] = din[10] ^ din[8];
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dout[11] = din[9] ^ din[7];
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dout[10] = din[8] ^ din[6];
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dout[9] = din[7] ^ din[5];
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dout[8] = din[6] ^ din[4];
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dout[7] = din[5] ^ din[3];
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dout[6] = din[4] ^ din[2];
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dout[5] = din[3] ^ din[1];
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dout[4] = din[2] ^ din[0];
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dout[3] = din[1] ^ din[14] ^ din[13];
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dout[2] = din[0] ^ din[13] ^ din[12];
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dout[1] = din[14] ^ din[12] ^ din[13] ^ din[11];
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dout[0] = din[13] ^ din[11] ^ din[12] ^ din[10];
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pn = dout;
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end
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endfunction
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always @(posedge clk) begin
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status <= {24'h0, RP_ID};
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mode <= control[7:4];
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end
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// sine tone generation
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always @(posedge clk) begin
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if (dst_dac_en == 1'h1) begin
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counter <= counter + 1;
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end
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end
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always @(counter) begin
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case(counter)
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3'd0 : begin
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sin_tone <= 16'h0000;
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cos_tone <= 16'h7FFF;
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end
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3'd1 : begin
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sin_tone <= 16'h5A82;
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cos_tone <= 16'h5A82;
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end
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3'd2 : begin
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sin_tone <= 16'h7FFF;
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cos_tone <= 16'h0000;
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end
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3'd3 : begin
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sin_tone <= 16'h5A82;
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cos_tone <= 16'hA57E;
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end
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3'd4 : begin
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sin_tone <= 16'h0000;
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cos_tone <= 16'h8001;
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end
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3'd5 : begin
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sin_tone <= 16'hA57E;
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cos_tone <= 16'hA57E;
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end
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3'd6 : begin
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sin_tone <= 16'h8001;
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cos_tone <= 16'h0000;
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end
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3'd7 : begin
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sin_tone <= 16'hA57E;
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cos_tone <= 16'h5A82;
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end
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endcase
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end
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// prbs generation
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always @(posedge clk) begin
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if(dst_dac_en == 1'h1) begin
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dac_prbs <= pn(dac_prbs);
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end
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end
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// constant pattern generator
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always @(posedge clk) begin
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if(dst_dac_en == 1'h1) begin
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pattern <= ~pattern;
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end
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end
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assign dac_pattern_s = (pattern == 1'h1) ?
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{16'h5555, 16'hAAAA, 16'h5555, 16'hAAAA} :
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{16'hAAAA, 16'h5555, 16'hAAAA, 16'h5555};
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// output mux for tx side
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always @(posedge clk) begin
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src_dac_en <= (mode == 0) ? dst_dac_en : 1'b0;
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dst_dac_dvalid <= (mode == 0) ? src_dac_dvalid : dst_dac_en;
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dst_dac_dunf <= (mode == 0) ? src_dac_dunf : 1'b0;
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end
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always @(posedge clk) begin
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case(mode)
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4'h0 : begin
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dst_dac_ddata <= src_dac_ddata;
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end
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4'h1 : begin
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dst_dac_ddata <= {cos_tone, sin_tone};
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end
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4'h2 : begin
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dst_dac_ddata <= dac_prbs;
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end
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4'h3 : begin
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dst_dac_ddata <= dac_pattern_s;
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end
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default : begin
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dst_dac_ddata <= src_dac_ddata;
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end
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endcase
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end
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endmodule
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