261 lines
8.6 KiB
Tcl
261 lines
8.6 KiB
Tcl
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# TODO: This works only up to 4 lanes on 64B66B
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proc create_versal_phy {
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{ip_name versal_phy}
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{num_lanes 2}
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{rx_lane_rate 11.88}
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{tx_lane_rate 11.88}
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{ref_clock 360}
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} {
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set num_quads [expr round(1.0*$num_lanes/4)]
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set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / 66]]
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set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / 66]]
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create_bd_cell -type hier ${ip_name}
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# Common interface
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create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk
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create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk
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create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk
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create_bd_pin -dir I ${ip_name}/apb3clk -type clk
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create_bd_pin -dir I ${ip_name}/reset_rx_pll_and_datapath_in
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create_bd_pin -dir I ${ip_name}/reset_tx_pll_and_datapath_in
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ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_0
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set_property -dict [list \
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CONFIG.BYPASS_MODE {true} \
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CONFIG.IP_NO_OF_LANES ${num_lanes} \
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CONFIG.IP_PRESET {GTY-JESD204_64B66B} \
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CONFIG.IP_LR0_SETTINGS [list \
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PRESET GTY-JESD204_64B66B \
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INTERNAL_PRESET JESD204_64B66B \
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GT_TYPE GTY \
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GT_DIRECTION DUPLEX \
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TX_LINE_RATE $tx_lane_rate \
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TX_PLL_TYPE LCPLL \
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TX_REFCLK_FREQUENCY $ref_clock \
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TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
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TX_FRACN_ENABLED true \
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TX_FRACN_NUMERATOR 0 \
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TX_REFCLK_SOURCE R0 \
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TX_DATA_ENCODING 64B66B_ASYNC \
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TX_USER_DATA_WIDTH 64 \
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TX_INT_DATA_WIDTH 64 \
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TX_BUFFER_MODE 1 \
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TX_BUFFER_BYPASS_MODE Fast_Sync \
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TX_PIPM_ENABLE false \
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TX_OUTCLK_SOURCE TXPROGDIVCLK \
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TXPROGDIV_FREQ_ENABLE true \
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TXPROGDIV_FREQ_SOURCE LCPLL \
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TXPROGDIV_FREQ_VAL $tx_progdiv_clock \
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TX_DIFF_SWING_EMPH_MODE CUSTOM \
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TX_64B66B_SCRAMBLER false \
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TX_64B66B_ENCODER false \
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TX_64B66B_CRC false \
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TX_RATE_GROUP A \
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RX_LINE_RATE $rx_lane_rate \
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RX_PLL_TYPE LCPLL \
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RX_REFCLK_FREQUENCY $ref_clock \
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RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
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RX_FRACN_ENABLED true \
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RX_FRACN_NUMERATOR 0 \
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RX_REFCLK_SOURCE R0 \
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RX_DATA_DECODING 64B66B_ASYNC \
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RX_USER_DATA_WIDTH 64 \
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RX_INT_DATA_WIDTH 64 \
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RX_BUFFER_MODE 1 \
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RX_OUTCLK_SOURCE RXPROGDIVCLK \
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RXPROGDIV_FREQ_ENABLE true \
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RXPROGDIV_FREQ_SOURCE LCPLL \
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RXPROGDIV_FREQ_VAL $rx_progdiv_clock \
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INS_LOSS_NYQ 12 \
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RX_EQ_MODE LPM \
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RX_COUPLING AC \
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RX_TERMINATION PROGRAMMABLE \
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RX_RATE_GROUP A \
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RX_TERMINATION_PROG_VALUE 800 \
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RX_PPM_OFFSET 0 \
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RX_64B66B_DESCRAMBLER false \
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RX_64B66B_DECODER false \
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RX_64B66B_CRC false \
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OOB_ENABLE false \
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RX_COMMA_ALIGN_WORD 1 \
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RX_COMMA_SHOW_REALIGN_ENABLE true \
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PCIE_ENABLE false \
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RX_COMMA_P_ENABLE false \
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RX_COMMA_M_ENABLE false \
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RX_COMMA_DOUBLE_ENABLE false \
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RX_COMMA_P_VAL 0101111100 \
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RX_COMMA_M_VAL 1010000011 \
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RX_COMMA_MASK 0000000000 \
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RX_SLIDE_MODE OFF \
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RX_SSC_PPM 0 \
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RX_CB_NUM_SEQ 0 \
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RX_CB_LEN_SEQ 1 \
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RX_CB_MAX_SKEW 1 \
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RX_CB_MAX_LEVEL 1 \
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RX_CB_MASK_0_0 false \
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RX_CB_VAL_0_0 00000000 \
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RX_CB_K_0_0 false \
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RX_CB_DISP_0_0 false \
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RX_CB_MASK_0_1 false \
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RX_CB_VAL_0_1 00000000 \
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RX_CB_K_0_1 false \
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RX_CB_DISP_0_1 false \
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RX_CB_MASK_0_2 false \
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RX_CB_VAL_0_2 00000000 \
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RX_CB_K_0_2 false \
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RX_CB_DISP_0_2 false \
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RX_CB_MASK_0_3 false \
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RX_CB_VAL_0_3 00000000 \
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RX_CB_K_0_3 false \
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RX_CB_DISP_0_3 false \
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RX_CB_MASK_1_0 false \
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RX_CB_VAL_1_0 00000000 \
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RX_CB_K_1_0 false \
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RX_CB_DISP_1_0 false \
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RX_CB_MASK_1_1 false \
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RX_CB_VAL_1_1 00000000 \
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RX_CB_K_1_1 false \
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RX_CB_DISP_1_1 false \
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RX_CB_MASK_1_2 false \
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RX_CB_VAL_1_2 00000000 \
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RX_CB_K_1_2 false \
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RX_CB_DISP_1_2 false \
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RX_CB_MASK_1_3 false \
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RX_CB_VAL_1_3 00000000 \
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RX_CB_K_1_3 false \
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RX_CB_DISP_1_3 false \
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RX_CC_NUM_SEQ 0 \
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RX_CC_LEN_SEQ 1 \
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RX_CC_PERIODICITY 5000 \
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RX_CC_KEEP_IDLE DISABLE \
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RX_CC_PRECEDENCE ENABLE \
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RX_CC_REPEAT_WAIT 0 \
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RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \
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RX_CC_MASK_0_0 false \
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RX_CC_VAL_0_0 00000000 \
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RX_CC_K_0_0 false \
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RX_CC_DISP_0_0 false \
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RX_CC_MASK_0_1 false \
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RX_CC_VAL_0_1 00000000 \
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RX_CC_K_0_1 false \
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RX_CC_DISP_0_1 false \
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RX_CC_MASK_0_2 false \
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RX_CC_VAL_0_2 00000000 \
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RX_CC_K_0_2 false \
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RX_CC_DISP_0_2 false \
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RX_CC_MASK_0_3 false \
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RX_CC_VAL_0_3 00000000 \
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RX_CC_K_0_3 false \
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RX_CC_DISP_0_3 false \
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RX_CC_MASK_1_0 false \
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RX_CC_VAL_1_0 00000000 \
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RX_CC_K_1_0 false \
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RX_CC_DISP_1_0 false \
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RX_CC_MASK_1_1 false \
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RX_CC_VAL_1_1 00000000 \
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RX_CC_K_1_1 false \
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RX_CC_DISP_1_1 false \
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RX_CC_MASK_1_2 false \
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RX_CC_VAL_1_2 00000000 \
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RX_CC_K_1_2 false \
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RX_CC_DISP_1_2 false \
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RX_CC_MASK_1_3 false \
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RX_CC_VAL_1_3 00000000 \
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RX_CC_K_1_3 false \
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RX_CC_DISP_1_3 false \
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PCIE_USERCLK2_FREQ 250 \
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PCIE_USERCLK_FREQ 250 \
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RX_JTOL_FC 10 \
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RX_JTOL_LF_SLOPE -20 \
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RX_BUFFER_BYPASS_MODE Fast_Sync \
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RX_BUFFER_BYPASS_MODE_LANE MULTI \
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RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \
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RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \
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RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \
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TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \
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RESET_SEQUENCE_INTERVAL 0 \
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RX_COMMA_PRESET NONE \
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RX_COMMA_VALID_ONLY 0 \
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] \
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] [get_bd_cells ${ip_name}/gt_bridge_ip_0]
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ad_ip_instance gt_quad_base ${ip_name}/gt_quad_base_0
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 ${ip_name}/GT_Serial
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ad_connect ${ip_name}/gt_quad_base_0/GT_Serial ${ip_name}/GT_Serial
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ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx
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ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx
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ad_connect ${ip_name}/gt_quad_base_0/ch0_rxoutclk ${ip_name}/bufg_gt_rx/outclk
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ad_connect ${ip_name}/gt_quad_base_0/ch0_txoutclk ${ip_name}/bufg_gt_tx/outclk
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ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_bridge_ip_0/gt_rxusrclk
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ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_bridge_ip_0/gt_txusrclk
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ad_connect ${ip_name}/gt_bridge_ip_0/rxusrclk_out ${ip_name}/rxusrclk_out
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ad_connect ${ip_name}/gt_bridge_ip_0/txusrclk_out ${ip_name}/txusrclk_out
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for {set j 0} {$j < $num_lanes} {incr j} {
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ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j}
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ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_TX${j}_EXT
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# TODO: This works only up to 4 lanes
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ad_connect ${ip_name}/gt_bridge_ip_0/GT_TX${j} ${ip_name}/gt_quad_base_0/TX${j}_GT_IP_Interface
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j}
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ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX
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ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/tx_adapt_${j}/usr_clk
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}
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for {set j 0} {$j < $num_lanes} {incr j} {
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ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j}
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ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_RX${j}_EXT
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# TODO: This works only up to 4 lanes
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ad_connect ${ip_name}/gt_bridge_ip_0/GT_RX${j} ${ip_name}/gt_quad_base_0/RX${j}_GT_IP_Interface
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create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j}
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ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX
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ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/rx_adapt_${j}/usr_clk
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}
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for {set i 0} {$i < $num_quads} {incr i} {
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for {set j 0} {$j < 4} {incr j} {
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ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_rxusrclk
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ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_txusrclk
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}
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}
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# Clocks and resets
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ad_connect ${ip_name}/apb3clk ${ip_name}/gt_bridge_ip_0/apb3clk
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ad_connect GND ${ip_name}/gt_bridge_ip_0/gtreset_in
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ad_connect ${ip_name}/reset_rx_pll_and_datapath_in ${ip_name}/gt_bridge_ip_0/reset_rx_pll_and_datapath_in
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ad_connect ${ip_name}/reset_tx_pll_and_datapath_in ${ip_name}/gt_bridge_ip_0/reset_tx_pll_and_datapath_in
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ad_ip_instance xlconcat ${ip_name}/xlconcat_0 [list \
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NUM_PORTS $num_quads \
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]
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ad_ip_instance util_reduced_logic ${ip_name}/util_reduced_logic_0 [list \
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C_SIZE $num_quads \
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]
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for {set j 0} {$j < $num_quads} {incr j} {
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ad_connect ${ip_name}/xlconcat_0/In${j} ${ip_name}/gt_quad_base_${j}/gtpowergood
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ad_connect ${ip_name}/apb3clk ${ip_name}/gt_quad_base_${j}/apb3clk
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ad_connect ${ip_name}/GT_REFCLK ${ip_name}/gt_quad_base_${j}/GT_REFCLK0
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}
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ad_connect ${ip_name}/xlconcat_0/dout ${ip_name}/util_reduced_logic_0/Op1
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ad_connect ${ip_name}/util_reduced_logic_0/Res ${ip_name}/gt_bridge_ip_0/gtpowergood
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}
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