648 lines
23 KiB
Verilog
648 lines
23 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns / 1ps
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module axi_ad9162_channel (
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// dac interface
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dac_clk,
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dac_rst,
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dac_enable,
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dac_data,
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dma_data,
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// processor interface
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dac_data_sync,
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dac_dds_format,
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// bus interface
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up_rstn,
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up_clk,
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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parameter CHANNEL_ID = 32'h0;
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parameter DATAPATH_DISABLE = 0;
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// dac interface
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input dac_clk;
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input dac_rst;
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output dac_enable;
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output [255:0] dac_data;
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input [255:0] dma_data;
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// processor interface
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input dac_data_sync;
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input dac_dds_format;
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// bus interface
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input up_rstn;
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input up_clk;
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input up_wreq;
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input [ 13:0] up_waddr;
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input [ 31:0] up_wdata;
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output up_wack;
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input up_rreq;
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input [ 13:0] up_raddr;
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output [ 31:0] up_rdata;
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output up_rack;
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// internal registers
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reg dac_enable = 'd0;
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reg [255:0] dac_data = 'd0;
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reg [255:0] dac_pn7_data = 'd0;
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reg [255:0] dac_pn15_data = 'd0;
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reg [ 15:0] dac_dds_phase_00_0 = 'd0;
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reg [ 15:0] dac_dds_phase_00_1 = 'd0;
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reg [ 15:0] dac_dds_phase_01_0 = 'd0;
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reg [ 15:0] dac_dds_phase_01_1 = 'd0;
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reg [ 15:0] dac_dds_phase_02_0 = 'd0;
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reg [ 15:0] dac_dds_phase_02_1 = 'd0;
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reg [ 15:0] dac_dds_phase_03_0 = 'd0;
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reg [ 15:0] dac_dds_phase_03_1 = 'd0;
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reg [ 15:0] dac_dds_phase_04_0 = 'd0;
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reg [ 15:0] dac_dds_phase_04_1 = 'd0;
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reg [ 15:0] dac_dds_phase_05_0 = 'd0;
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reg [ 15:0] dac_dds_phase_05_1 = 'd0;
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reg [ 15:0] dac_dds_phase_06_0 = 'd0;
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reg [ 15:0] dac_dds_phase_06_1 = 'd0;
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reg [ 15:0] dac_dds_phase_07_0 = 'd0;
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reg [ 15:0] dac_dds_phase_07_1 = 'd0;
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reg [ 15:0] dac_dds_phase_08_0 = 'd0;
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reg [ 15:0] dac_dds_phase_08_1 = 'd0;
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reg [ 15:0] dac_dds_phase_09_0 = 'd0;
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reg [ 15:0] dac_dds_phase_09_1 = 'd0;
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reg [ 15:0] dac_dds_phase_10_0 = 'd0;
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reg [ 15:0] dac_dds_phase_10_1 = 'd0;
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reg [ 15:0] dac_dds_phase_11_0 = 'd0;
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reg [ 15:0] dac_dds_phase_11_1 = 'd0;
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reg [ 15:0] dac_dds_phase_12_0 = 'd0;
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reg [ 15:0] dac_dds_phase_12_1 = 'd0;
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reg [ 15:0] dac_dds_phase_13_0 = 'd0;
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reg [ 15:0] dac_dds_phase_13_1 = 'd0;
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reg [ 15:0] dac_dds_phase_14_0 = 'd0;
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reg [ 15:0] dac_dds_phase_14_1 = 'd0;
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reg [ 15:0] dac_dds_phase_15_0 = 'd0;
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reg [ 15:0] dac_dds_phase_15_1 = 'd0;
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reg [ 15:0] dac_dds_incr_0 = 'd0;
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reg [ 15:0] dac_dds_incr_1 = 'd0;
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reg [255:0] dac_dds_data = 'd0;
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// internal signals
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wire [ 15:0] dac_dds_scale_1_s;
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wire [ 15:0] dac_dds_init_1_s;
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wire [ 15:0] dac_dds_incr_1_s;
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wire [ 15:0] dac_dds_scale_2_s;
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wire [ 15:0] dac_dds_init_2_s;
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wire [ 15:0] dac_dds_incr_2_s;
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wire [ 15:0] dac_pat_data_1_s;
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wire [ 15:0] dac_pat_data_2_s;
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wire [ 3:0] dac_data_sel_s;
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wire dac_iq_mode_s;
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wire [255:0] dac_pn7_data_i_s;
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wire [255:0] dac_pn15_data_i_s;
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wire [255:0] dac_pn7_data_s;
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wire [255:0] dac_pn15_data_s;
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wire [255:0] dac_pat_data_s;
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wire [255:0] dac_dds_data_s;
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genvar n;
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// PN7 function
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function [255:0] pn7;
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input [7:0] din;
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reg [255:0] dout;
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reg [15:0] dout16;
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reg [7:0] din_reg;
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integer i;
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integer j;
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begin
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din_reg = din;
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for ( j=0 ; j<16 ; j=j+1)begin
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for ( i=0 ; i<16 ; i= i+1)begin
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din_reg = {din_reg,din_reg[6]^din_reg[5]};
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dout16[15-i] = din_reg[0];
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end
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dout = {dout16,dout[255:16]};
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end
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pn7 = dout;
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end
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endfunction
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// PN15 function
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function [255:0] pn15;
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input [15:0] din;
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reg [255:0] dout;
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reg [15:0] dout16;
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reg [15:0] din_reg;
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integer i;
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integer j;
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begin
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din_reg = din;
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for (j=0 ; j<16 ; j=j+1)begin
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for (i=0 ; i<16 ; i= i+1)begin
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din_reg = {din_reg,din_reg[14]^din_reg[13]};
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dout16[15-i] = din_reg[0];
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end
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dout = {dout16,dout[255:16]};
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end
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pn15 = dout;
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end
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endfunction
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assign dac_pn7_data_i_s = ~dac_pn7_data;
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assign dac_pn15_data_i_s = ~dac_pn15_data;
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assign dac_pn7_data_s = dac_pn7_data;
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assign dac_pn15_data_s = dac_pn15_data;
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generate
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for (n = 0; n < 8; n = n + 1) begin: g_dac_pat_data
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assign dac_pat_data_s[((32*n)+31):((32*n)+16)] = dac_pat_data_2_s;
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assign dac_pat_data_s[((32*n)+15):((32*n)+ 0)] = dac_pat_data_1_s;
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end
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endgenerate
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// dac data select
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always @(posedge dac_clk) begin
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dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
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case (dac_data_sel_s)
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4'h7: dac_data <= dac_pn15_data_s;
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4'h6: dac_data <= dac_pn7_data_s;
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4'h5: dac_data <= dac_pn15_data_i_s;
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4'h4: dac_data <= dac_pn7_data_i_s;
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4'h3: dac_data <= 256'd0;
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4'h2: dac_data <= dma_data;
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4'h1: dac_data <= dac_pat_data_s;
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default: dac_data <= dac_dds_data;
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endcase
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end
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// pn registers
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always @(posedge dac_clk) begin
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if (dac_data_sync == 1'b1) begin
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dac_pn7_data <= {255{1'd1}};
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dac_pn15_data <= {255{1'd1}};
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end else begin
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dac_pn7_data <= pn7(dac_pn7_data[247:240]);
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dac_pn15_data <= pn15(dac_pn15_data[255:240]);
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end
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end
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// dds
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always @(posedge dac_clk) begin
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if (dac_data_sync == 1'b0) begin
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dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0;
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dac_dds_phase_00_1 <= dac_dds_phase_00_1 + dac_dds_incr_1;
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dac_dds_phase_01_0 <= dac_dds_phase_01_0 + dac_dds_incr_0;
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dac_dds_phase_01_1 <= dac_dds_phase_01_1 + dac_dds_incr_1;
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dac_dds_phase_02_0 <= dac_dds_phase_02_0 + dac_dds_incr_0;
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dac_dds_phase_02_1 <= dac_dds_phase_02_1 + dac_dds_incr_1;
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dac_dds_phase_03_0 <= dac_dds_phase_03_0 + dac_dds_incr_0;
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dac_dds_phase_03_1 <= dac_dds_phase_03_1 + dac_dds_incr_1;
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dac_dds_phase_04_0 <= dac_dds_phase_04_0 + dac_dds_incr_0;
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dac_dds_phase_04_1 <= dac_dds_phase_04_1 + dac_dds_incr_1;
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dac_dds_phase_05_0 <= dac_dds_phase_05_0 + dac_dds_incr_0;
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dac_dds_phase_05_1 <= dac_dds_phase_05_1 + dac_dds_incr_1;
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dac_dds_phase_06_0 <= dac_dds_phase_06_0 + dac_dds_incr_0;
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dac_dds_phase_06_1 <= dac_dds_phase_06_1 + dac_dds_incr_1;
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dac_dds_phase_07_0 <= dac_dds_phase_07_0 + dac_dds_incr_0;
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dac_dds_phase_07_1 <= dac_dds_phase_07_1 + dac_dds_incr_1;
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dac_dds_phase_08_0 <= dac_dds_phase_08_0 + dac_dds_incr_0;
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dac_dds_phase_08_1 <= dac_dds_phase_08_1 + dac_dds_incr_1;
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dac_dds_phase_09_0 <= dac_dds_phase_09_0 + dac_dds_incr_0;
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dac_dds_phase_09_1 <= dac_dds_phase_09_1 + dac_dds_incr_1;
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dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_0;
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dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_1;
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dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_0;
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dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_1;
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dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_0;
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dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_1;
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dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_0;
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dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_1;
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dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_0;
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dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_1;
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dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_0;
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dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_1;
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dac_dds_incr_0 <= dac_dds_incr_0;
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dac_dds_incr_1 <= dac_dds_incr_1;
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dac_dds_data <= dac_dds_data_s;
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end else if (dac_iq_mode_s == 1'b1) begin
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dac_dds_phase_00_0 <= dac_dds_init_1_s;
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dac_dds_phase_00_1 <= dac_dds_init_2_s;
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dac_dds_phase_01_0 <= dac_dds_phase_00_0 + 16'h4000;
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dac_dds_phase_01_1 <= dac_dds_phase_00_1 + 16'h4000;
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dac_dds_phase_02_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
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dac_dds_phase_02_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
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dac_dds_phase_03_0 <= dac_dds_phase_02_0 + 16'h4000;
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dac_dds_phase_03_1 <= dac_dds_phase_02_1 + 16'h4000;
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dac_dds_phase_04_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
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dac_dds_phase_04_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
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dac_dds_phase_05_0 <= dac_dds_phase_04_0 + 16'h4000;
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dac_dds_phase_05_1 <= dac_dds_phase_04_1 + 16'h4000;
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dac_dds_phase_06_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
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dac_dds_phase_06_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
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dac_dds_phase_07_0 <= dac_dds_phase_06_0 + 16'h4000;
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dac_dds_phase_07_1 <= dac_dds_phase_06_1 + 16'h4000;
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dac_dds_phase_08_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
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dac_dds_phase_08_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
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dac_dds_phase_09_0 <= dac_dds_phase_08_0 + 16'h4000;
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dac_dds_phase_09_1 <= dac_dds_phase_08_1 + 16'h4000;
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dac_dds_phase_10_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
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dac_dds_phase_10_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
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dac_dds_phase_11_0 <= dac_dds_phase_10_0 + 16'h4000;
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dac_dds_phase_11_1 <= dac_dds_phase_10_1 + 16'h4000;
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dac_dds_phase_12_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
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dac_dds_phase_12_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
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dac_dds_phase_13_0 <= dac_dds_phase_12_0 + 16'h4000;
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dac_dds_phase_13_1 <= dac_dds_phase_12_1 + 16'h4000;
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dac_dds_phase_14_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
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dac_dds_phase_14_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
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dac_dds_phase_15_0 <= dac_dds_phase_14_0 + 16'h4000;
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dac_dds_phase_15_1 <= dac_dds_phase_14_1 + 16'h4000;
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dac_dds_incr_0 <= {dac_dds_incr_1_s[12:0], 3'd0};
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dac_dds_incr_1 <= {dac_dds_incr_2_s[12:0], 3'd0};
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dac_dds_data <= 256'd0;
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end else begin
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dac_dds_phase_00_0 <= dac_dds_init_1_s;
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dac_dds_phase_00_1 <= dac_dds_init_2_s;
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dac_dds_phase_01_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
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dac_dds_phase_01_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
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dac_dds_phase_02_0 <= dac_dds_phase_01_0 + dac_dds_incr_1_s;
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dac_dds_phase_02_1 <= dac_dds_phase_01_1 + dac_dds_incr_2_s;
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dac_dds_phase_03_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
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dac_dds_phase_03_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
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dac_dds_phase_04_0 <= dac_dds_phase_03_0 + dac_dds_incr_1_s;
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dac_dds_phase_04_1 <= dac_dds_phase_03_1 + dac_dds_incr_2_s;
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dac_dds_phase_05_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
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dac_dds_phase_05_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
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dac_dds_phase_06_0 <= dac_dds_phase_05_0 + dac_dds_incr_1_s;
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dac_dds_phase_06_1 <= dac_dds_phase_05_1 + dac_dds_incr_2_s;
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dac_dds_phase_07_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
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dac_dds_phase_07_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
|
|
dac_dds_phase_08_0 <= dac_dds_phase_07_0 + dac_dds_incr_1_s;
|
|
dac_dds_phase_08_1 <= dac_dds_phase_07_1 + dac_dds_incr_2_s;
|
|
dac_dds_phase_09_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
|
|
dac_dds_phase_09_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
|
|
dac_dds_phase_10_0 <= dac_dds_phase_09_0 + dac_dds_incr_1_s;
|
|
dac_dds_phase_10_1 <= dac_dds_phase_09_1 + dac_dds_incr_2_s;
|
|
dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
|
|
dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
|
|
dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
|
|
dac_dds_phase_12_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s;
|
|
dac_dds_phase_13_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
|
|
dac_dds_phase_13_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
|
|
dac_dds_phase_14_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s;
|
|
dac_dds_phase_14_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s;
|
|
dac_dds_phase_15_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s;
|
|
dac_dds_phase_15_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s;
|
|
dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0};
|
|
dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0};
|
|
dac_dds_data <= 256'd0;
|
|
end
|
|
end
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[15:0] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_00 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_00_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_00_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[15:0]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[31:16] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_01 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_01_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_01_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[31:16]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[47:32] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_02 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_02_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_02_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[47:32]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[63:48] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_03 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_03_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_03_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[63:48]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[79:64] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_04 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_04_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_04_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[79:64]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[95:80] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_05 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_05_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_05_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[95:80]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[111:96] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_06 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_06_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_06_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[111:96]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[127:112] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_07 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_07_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_07_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[127:112]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[143:128] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_08 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_08_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_08_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[143:128]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[159:144] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_09 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_09_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_09_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[159:144]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[175:160] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_10 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_10_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_10_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[175:160]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[191:176] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_11 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_11_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_11_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[191:176]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[207:192] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_12 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_12_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_12_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[207:192]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[223:208] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_13 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_13_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_13_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[223:208]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[239:224] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_14 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_14_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_14_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[239:224]));
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DATAPATH_DISABLE == 1) begin
|
|
assign dac_dds_data_s[255:240] = 16'd0;
|
|
end else begin
|
|
ad_dds i_dds_15 (
|
|
.clk (dac_clk),
|
|
.dds_format (dac_dds_format),
|
|
.dds_phase_0 (dac_dds_phase_15_0),
|
|
.dds_scale_0 (dac_dds_scale_1_s),
|
|
.dds_phase_1 (dac_dds_phase_15_1),
|
|
.dds_scale_1 (dac_dds_scale_2_s),
|
|
.dds_data (dac_dds_data_s[255:240]));
|
|
end
|
|
endgenerate
|
|
|
|
// single channel processor
|
|
|
|
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
|
|
.dac_clk (dac_clk),
|
|
.dac_rst (dac_rst),
|
|
.dac_dds_scale_1 (dac_dds_scale_1_s),
|
|
.dac_dds_init_1 (dac_dds_init_1_s),
|
|
.dac_dds_incr_1 (dac_dds_incr_1_s),
|
|
.dac_dds_scale_2 (dac_dds_scale_2_s),
|
|
.dac_dds_init_2 (dac_dds_init_2_s),
|
|
.dac_dds_incr_2 (dac_dds_incr_2_s),
|
|
.dac_pat_data_1 (dac_pat_data_1_s),
|
|
.dac_pat_data_2 (dac_pat_data_2_s),
|
|
.dac_data_sel (dac_data_sel_s),
|
|
.dac_iq_mode (dac_iq_mode_s),
|
|
.dac_iqcor_enb (),
|
|
.dac_iqcor_coeff_1 (),
|
|
.dac_iqcor_coeff_2 (),
|
|
.up_usr_datatype_be (),
|
|
.up_usr_datatype_signed (),
|
|
.up_usr_datatype_shift (),
|
|
.up_usr_datatype_total_bits (),
|
|
.up_usr_datatype_bits (),
|
|
.up_usr_interpolation_m (),
|
|
.up_usr_interpolation_n (),
|
|
.dac_usr_datatype_be (1'b0),
|
|
.dac_usr_datatype_signed (1'b1),
|
|
.dac_usr_datatype_shift (8'd0),
|
|
.dac_usr_datatype_total_bits (8'd16),
|
|
.dac_usr_datatype_bits (8'd16),
|
|
.dac_usr_interpolation_m (16'd1),
|
|
.dac_usr_interpolation_n (16'd1),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq),
|
|
.up_waddr (up_waddr),
|
|
.up_wdata (up_wdata),
|
|
.up_wack (up_wack),
|
|
.up_rreq (up_rreq),
|
|
.up_raddr (up_raddr),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|