pluto_hdl_adi/library/xilinx
Lars-Peter Clausen 7f18fc5f1c axi_dacfifo: Add missing read-enable signal to ad_mem instance
Commit bfc8ec28c3 ("util_axis_fifo: instantiate block ram in async mode")
added the read-enable (reb) signal to the ad_mem block.

It didn't update the ad_mem instance in axi_dacfifo_address_buffer.v. This
results in the read-enable of the address_buffer being tied to 0.

Fix this by connecting the same signal that increments the read address.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-11 09:55:07 +02:00
..
axi_adcfifo Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_adxcvr Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
axi_dacfifo axi_dacfifo: Add missing read-enable signal to ad_mem instance 2018-06-11 09:55:07 +02:00
axi_xcvrlb Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
common Move Xilinx specific DC filter implementation to library/xilinx/common/ 2018-04-11 15:09:54 +03:00
util_adxcvr xilinx: util_adxcvr: Add support for lane polarity inversion 2018-05-02 09:37:23 +02:00