79 lines
5.6 KiB
Plaintext
79 lines
5.6 KiB
Plaintext
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create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}]
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create_clock -period 4.0 -name rx_clk [get_ports {rx_clk_in}]
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derive_pll_clocks
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derive_clock_uncertainty
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create_clock -period 4.0 -name v_rx_clk
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set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
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set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
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set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
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set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
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set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
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set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
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set_input_delay -add_delay -rise -max 1.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
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set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
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set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
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set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
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set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
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set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
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set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
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set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
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set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
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set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
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set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
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set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
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set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
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set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
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set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
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set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
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set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
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set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
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set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
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set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
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set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
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set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
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create_generated_clock -name v_tx_clk_reg \
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-source [get_pins -hierarchical *counter\[0\]*divclk*] \
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[get_registers *ad_serdes_tx_clock_out*TX_OUTPUT_DFF*]
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create_generated_clock -name v_tx_clk \
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-source [get_registers *ad_serdes_tx_clock_out*TX_OUTPUT_DFF*] \
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[get_ports {tx_clk_out}]
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set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
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set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
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set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
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set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
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set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
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set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
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set_output_delay -add_delay -rise -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
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set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
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set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
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set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
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set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
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set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
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set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
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set_output_delay -add_delay -rise -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
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set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
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set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
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set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
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set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
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set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
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set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
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set_output_delay -add_delay -fall -max 1.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
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set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_frame_out}]
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set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[0]}]
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set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[1]}]
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set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[2]}]
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set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[3]}]
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set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[4]}]
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set_output_delay -add_delay -fall -min 0.2 -clock {v_tx_clk} [get_ports {tx_data_out[5]}]
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# frame reader seems to use the wrong reset!
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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