58 lines
716 B
Verilog
58 lines
716 B
Verilog
// HIERARCHY
|
|
// ENDHIERARCHY
|
|
|
|
`ifndef xlConvPkgIncluded
|
|
`define xlConvPkgIncluded 1
|
|
`endif
|
|
|
|
// synopsys translate_off
|
|
`ifndef simulating
|
|
`define simulating 1
|
|
`endif
|
|
// synopsys translate_on
|
|
|
|
|
|
`ifndef simulating
|
|
`define simulating 0
|
|
`endif
|
|
|
|
`ifndef xlUnsigned
|
|
`define xlUnsigned 1
|
|
`endif
|
|
|
|
`ifndef xlSigned
|
|
`define xlSigned 2
|
|
`endif
|
|
|
|
`ifndef xlFloat
|
|
`define xlFloat 3
|
|
`endif
|
|
|
|
`ifndef xlWrap
|
|
`define xlWrap 1
|
|
`endif
|
|
|
|
`ifndef xlSaturate
|
|
`define xlSaturate 2
|
|
`endif
|
|
|
|
`ifndef xlTruncate
|
|
`define xlTruncate 1
|
|
`endif
|
|
|
|
`ifndef xlRound
|
|
`define xlRound 2
|
|
`endif
|
|
|
|
`ifndef xlRoundBanker
|
|
`define xlRoundBanker 3
|
|
`endif
|
|
|
|
`ifndef xlAddMode
|
|
`define xlAddMode 1
|
|
`endif
|
|
|
|
`ifndef xlSubMode
|
|
`define xlSubMode 2
|
|
`endif
|