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Adrian Costina 816238bb6c fmcjesdadc:A5gt, decreased destination bus width for DMAs to 256. Increased DMA FIFO to 32 
With lower buswidth, if all 4 channels are captured some samples are lost
With fifo size of 64, there are timing violations in the DMAC
With this configuration, 65536 samples could be captured from all 4 channels with no sample lost
Because of the DMAC destination bus is 256, the number of samples to be captured must be a multiple of 16, otherwise the system will freeze. This will be corrected in software
 		2015-07-24 15:31:19 +03:00
library axi_dmac: Added C_FIFO_SIZE parameter 2015-07-24 15:30:10 +03:00
projects fmcjesdadc:A5gt, decreased destination bus width for DMAs to 256. Increased DMA FIFO to 32 2015-07-24 15:31:19 +03:00
.gitattributes Add .gitattributes file 2015-07-01 18:43:51 +02:00
.gitignore gitignore: add non-project stuff 2015-05-01 13:17:14 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md Update README.md 2015-05-20 17:38:08 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

##NOTE

Beware! This branch is just a realease candidate. Final release expected at end of June.

###Tools version:

###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

For support please visit our FPGA Reference Designs Support Community on EngineerZone.