816238bb6c
With lower buswidth, if all 4 channels are captured some samples are lost With fifo size of 64, there are timing violations in the DMAC With this configuration, 65536 samples could be captured from all 4 channels with no sample lost Because of the DMAC destination bus is 256, the number of samples to be captured must be a multiple of 16, otherwise the system will freeze. This will be corrected in software |
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| a5gt | ||
| a5soc | ||
| common | ||
| kc705 | ||
| vc707 | ||
| zc706 | ||
| Makefile | ||