81fa65cd51
+ avl_write_transfer_done_s is a redundant net + specify the net state explicitly on if statements + to define the edge of avl_mem_fetch_wr_address signal, its register and its second sync register should be used |
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README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects
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Each release has its own branch and master always synced with the latest release. To find out more information about the latest release please check the release notes. Every branch, which has dev in its name, is a development branch and should handle it accordingly.