Istvan Csomortani 81fa65cd51 avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr ... + avl_write_transfer_done_s is a redundant net + specify the net state explicitly on if statements + to define the edge of avl_mem_fetch_wr_address signal, its register and its second sync register should be used		2017-05-25 15:12:13 +03:00
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alt_serdes	altera- default to latest version	2017-05-12 13:25:17 -04:00
avl_adxcfg	all: Update license for all hdl source files	2017-05-17 11:52:08 +03:00
avl_adxcvr	altera- infer latest versions	2017-05-12 13:40:14 -04:00
avl_adxphy	all: Update license for all hdl source files	2017-05-17 11:52:08 +03:00
avl_dacfifo	avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr	2017-05-25 15:12:13 +03:00
axi_adxcvr	all: Update license for all hdl source files	2017-05-17 11:52:08 +03:00
common	altera/ad_mem_asym: Fix grounded bus for marco instance	2017-05-25 15:12:09 +03:00