96 lines
2.9 KiB
Verilog
96 lines
2.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_ad9361_tdd_if#(
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parameter LEVEL_OR_PULSE_N = 0) (
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// clock
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input clk,
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input rst,
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// control signals from the tdd control
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input tdd_rx_vco_en,
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input tdd_tx_vco_en,
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input tdd_rx_rf_en,
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input tdd_tx_rf_en,
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// device interface
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output ad9361_txnrx,
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output ad9361_enable,
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// interface status
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output [ 7:0] ad9361_tdd_status);
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localparam PULSE_MODE = 0;
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localparam LEVEL_MODE = 1;
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// internal registers
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reg tdd_rx_rf_en_d = 1'b0;
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reg tdd_tx_rf_en_d = 1'b0;
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reg tdd_vco_overlap = 1'b0;
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reg tdd_rf_overlap = 1'b0;
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wire ad9361_txnrx_s;
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wire ad9361_enable_s;
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// just one VCO can be enabled at a time
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assign ad9361_txnrx_s = tdd_tx_vco_en & ~tdd_rx_vco_en;
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always @(posedge clk) begin
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tdd_rx_rf_en_d <= tdd_rx_rf_en;
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tdd_tx_rf_en_d <= tdd_tx_rf_en;
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end
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assign ad9361_enable_s = (LEVEL_OR_PULSE_N == PULSE_MODE) ?
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((~tdd_rx_rf_en_d & tdd_rx_rf_en) | (tdd_rx_rf_en_d & ~tdd_rx_rf_en) |
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(~tdd_tx_rf_en_d & tdd_tx_rf_en) | (tdd_tx_rf_en_d & ~tdd_tx_rf_en)) :
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(tdd_rx_rf_en | tdd_tx_rf_en);
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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tdd_vco_overlap <= 1'b0;
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tdd_rf_overlap <= 1'b0;
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end else begin
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tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en;
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tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en;
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end
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end
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assign ad9361_tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap};
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assign ad9361_txnrx = ad9361_txnrx_s;
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assign ad9361_enable = ad9361_enable_s;
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endmodule
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