73 lines
2.2 KiB
Verilog
73 lines
2.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_extract #(
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parameter CHANNELS = 2,
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parameter DW = CHANNELS * 16) (
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input clk,
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input [DW-1:0] data_in,
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input [DW-1:0] data_in_trigger,
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input data_valid,
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output [DW-1:0] data_out,
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output reg trigger_out
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);
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// loop variables
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genvar n;
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reg trigger_d1;
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wire [15:0] trigger; // 16 maximum channels
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generate
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for (n = 0; n < CHANNELS; n = n + 1) begin: g_data_out
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assign data_out[(n+1)*16-1:n*16] = {data_in[(n*16)+14],data_in[(n*16)+14:n*16]};
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assign trigger[n] = data_in_trigger[(16*n)+15];
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end
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for (n = CHANNELS; n < 16; n = n + 1) begin: g_trigger_out
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assign trigger[n] = 1'b0;
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end
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endgenerate
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// compensate delay in the FIFO
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always @(posedge clk) begin
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if (data_valid == 1'b1) begin
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trigger_d1 <= |trigger;
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trigger_out <= trigger_d1;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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