386 lines
11 KiB
Verilog
386 lines
11 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_logic_analyzer (
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input clk,
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output clk_out,
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input [15:0] data_i,
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output reg [15:0] data_o,
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output [15:0] data_t,
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input [ 1:0] trigger_i,
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output reg adc_valid,
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output reg [15:0] adc_data,
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input [15:0] dac_data,
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input dac_valid,
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output reg dac_read,
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output trigger_out,
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output [31:0] fifo_depth,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 6:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 6:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// internal registers
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reg [15:0] data_m1 = 'd0;
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reg [15:0] data_r = 'd0;
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reg [ 1:0] trigger_m1 = 'd0;
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reg [ 1:0] trigger_m2 = 'd0;
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reg [31:0] downsampler_counter_la = 'd0;
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reg [31:0] upsampler_counter_pg = 'd0;
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reg sample_valid_la = 'd0;
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reg adc_valid_d1 = 'd0;
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reg adc_valid_d2 = 'd0;
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reg [15:0] io_selection; // 1 - input, 0 - output
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reg [31:0] delay_counter = 'd0;
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reg triggered = 'd0;
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reg up_triggered;
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reg up_triggered_d1;
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reg up_triggered_d2;
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reg up_triggered_set;
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reg up_triggered_reset;
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reg up_triggered_reset_d1;
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reg up_triggered_reset_d2;
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reg streaming_on;
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire [ 4:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_wack;
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wire up_wreq;
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wire up_rack;
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wire [31:0] up_rdata;
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wire up_rreq;
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wire [ 4:0] up_raddr;
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wire reset;
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wire [31:0] divider_counter_la;
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wire [31:0] divider_counter_pg;
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wire [17:0] edge_detect_enable;
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wire [17:0] rise_edge_enable;
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wire [17:0] fall_edge_enable;
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wire [17:0] low_level_enable;
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wire [17:0] high_level_enable;
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wire trigger_logic; // 0-OR,1-AND,2-XOR,3-NOR,4-NAND,5-NXOR
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wire clock_select;
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wire [15:0] overwrite_enable;
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wire [15:0] overwrite_data;
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wire [15:0] io_selection_s; // 1 - input, 0 - output
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wire [15:0] od_pp_n; // 0 - push/pull, 1 - open drain
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wire trigger_out_s;
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wire [31:0] trigger_delay;
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wire trigger_out_delayed;
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wire streaming;
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genvar i;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on;
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assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
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always @(posedge clk_out) begin
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if (trigger_delay == 0) begin
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if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin
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streaming_on <= 1'b1;
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end else if (streaming == 1'b0) begin
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streaming_on <= 1'b0;
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end
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end else begin
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if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_delayed == 1'b1) begin
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streaming_on <= 1'b1;
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end else if (streaming == 1'b0) begin
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streaming_on <= 1'b0;
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end
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end
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end
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin
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up_triggered_set <= 1'b1;
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end else if (up_triggered_reset == 1'b1) begin
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up_triggered_set <= 1'b0;
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end
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up_triggered_reset_d1 <= up_triggered;
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up_triggered_reset_d2 <= up_triggered_reset_d1;
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up_triggered_reset <= up_triggered_reset_d2;
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end
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always @(posedge up_clk) begin
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up_triggered_d1 <= up_triggered_set;
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up_triggered_d2 <= up_triggered_d1;
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up_triggered <= up_triggered_d2;
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end
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generate
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for (i = 0 ; i < 16; i = i + 1) begin
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assign data_t[i] = od_pp_n[i] ? io_selection[i] & !data_o[i] : io_selection[i];
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always @(posedge clk_out) begin
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data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i];
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end
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always @(posedge clk_out) begin
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if(dac_valid == 1'b1) begin
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data_r[i] <= dac_data[i];
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end
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if (io_selection_s[i] == 1'b1) begin
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io_selection[i] <= 1'b1;
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end else begin
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if(dac_valid == 1'b1 || overwrite_enable[i] == 1'b1) begin
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io_selection[i] <= 1'b0;
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end
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end
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end
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end
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endgenerate
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BUFGMUX_CTRL BUFGMUX_CTRL_inst (
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.O (clk_out),
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.I0 (clk),
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.I1 (data_i[0]),
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.S (clock_select));
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// synchronization
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always @(posedge clk_out) begin
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data_m1 <= data_i;
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trigger_m1 <= trigger_i;
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trigger_m2 <= trigger_m1;
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end
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// transfer data at clock frequency
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// if capture is enabled
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always @(posedge clk_out) begin
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adc_valid_d1 <= adc_valid_d2;
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adc_valid <= adc_valid_d1;
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if (sample_valid_la == 1'b1) begin
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adc_data <= data_m1;
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adc_valid_d2 <= 1'b1;
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end else begin
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adc_valid_d2 <= 1'b0;
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end
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end
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// downsampler logic analyzer
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always @(posedge clk_out) begin
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if (reset == 1'b1) begin
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sample_valid_la <= 1'b0;
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downsampler_counter_la <= 32'h0;
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end else begin
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if (downsampler_counter_la < divider_counter_la ) begin
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downsampler_counter_la <= downsampler_counter_la + 1;
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sample_valid_la <= 1'b0;
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end else begin
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downsampler_counter_la <= 32'h0;
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sample_valid_la <= 1'b1;
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end
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end
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end
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// upsampler pattern generator
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always @(posedge clk_out) begin
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if (reset == 1'b1) begin
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upsampler_counter_pg <= 32'h0;
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dac_read <= 1'b0;
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end else begin
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dac_read <= 1'b0;
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if (upsampler_counter_pg < divider_counter_pg) begin
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upsampler_counter_pg <= upsampler_counter_pg + 1;
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end else begin
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upsampler_counter_pg <= 32'h0;
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dac_read <= 1'b1;
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end
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end
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end
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always @(posedge clk_out) begin
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if(trigger_delay == 32'h0) begin
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delay_counter <= 32'h0;
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end else begin
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if (adc_valid == 1'b1) begin
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triggered <= trigger_out_s | triggered;
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if (delay_counter == 32'h0) begin
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delay_counter <= trigger_delay;
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triggered <= 1'b0;
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end else begin
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if(triggered == 1'b1 || trigger_out_s == 1'b1) begin
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delay_counter <= delay_counter - 1;
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end
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end
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end
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end
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end
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axi_logic_analyzer_trigger i_trigger (
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.clk (clk_out),
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.reset (reset),
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.data (adc_data),
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.data_valid(sample_valid_la),
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.trigger (trigger_m2),
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.edge_detect_enable (edge_detect_enable),
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.rise_edge_enable (rise_edge_enable),
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.fall_edge_enable (fall_edge_enable),
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.low_level_enable (low_level_enable),
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.high_level_enable (high_level_enable),
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.trigger_logic (trigger_logic),
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.trigger_out (trigger_out_s));
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axi_logic_analyzer_reg i_registers (
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.clk (clk_out),
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.reset (reset),
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.divider_counter_la (divider_counter_la),
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.divider_counter_pg (divider_counter_pg),
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.io_selection (io_selection_s),
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.edge_detect_enable (edge_detect_enable),
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.rise_edge_enable (rise_edge_enable),
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.fall_edge_enable (fall_edge_enable),
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.low_level_enable (low_level_enable),
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.high_level_enable (high_level_enable),
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.fifo_depth (fifo_depth),
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.trigger_delay (trigger_delay),
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.trigger_logic (trigger_logic),
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.clock_select (clock_select),
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.overwrite_enable (overwrite_enable),
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.overwrite_data (overwrite_data),
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.input_data (adc_data),
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.od_pp_n (od_pp_n),
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.triggered (up_triggered),
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.streaming(streaming),
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// bus interface
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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// axi interface
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up_axi #(
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.AXI_ADDRESS_WIDTH(7),
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.ADDRESS_WIDTH(5)
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) i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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