pluto_hdl_adi/projects/pzsdr1/ccbrk_cmos/system_top.v

222 lines
6.8 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout iic_scl,
inout iic_sda,
inout [10:0] gpio_bd,
input rx_clk_in,
input rx_frame_in,
input [11:0] rx_data_in,
output tx_clk_out,
output tx_frame_out,
output [11:0] tx_data_out,
output [ 1:0] tx_gnd,
output enable,
output txnrx,
input clkout_in,
output clkout_out,
inout gpio_clksel,
inout gpio_resetb,
inout gpio_sync,
inout gpio_en_agc,
inout [ 3:0] gpio_ctl,
inout [ 7:0] gpio_status,
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso,
output [27:0] gp_out,
input [27:0] gp_in);
// internal signals
wire [31:0] gp_out_s;
wire [31:0] gp_in_s;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// assignments
assign tx_gnd = 2'd0;
assign clkout_out = clkout_in;
assign gp_out[27:0] = gp_out_s[27:0];
assign gp_in_s[31:28] = gp_out_s[31:28];
assign gp_in_s[27: 0] = gp_in[27:0];
// board gpio - 31-0
assign gpio_i[31:11] = gpio_o[31:11];
ad_iobuf #(.DATA_WIDTH(11)) i_iobuf_bd (
.dio_t (gpio_t[10:0]),
.dio_i (gpio_o[10:0]),
.dio_o (gpio_i[10:0]),
.dio_p (gpio_bd));
// ad9361 gpio - 63-32
assign gpio_i[63:52] = gpio_o[63:52];
assign gpio_i[50:47] = gpio_o[50:47];
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
.dio_t ({gpio_t[51], gpio_t[46:32]}),
.dio_i ({gpio_o[51], gpio_o[46:32]}),
.dio_o ({gpio_i[51], gpio_i[46:32]}),
.dio_p ({ gpio_clksel, // 51:51
gpio_resetb, // 46:46
gpio_sync, // 45:45
gpio_en_agc, // 44:44
gpio_ctl, // 43:40
gpio_status})); // 39:32
// instantiations
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.enable (enable),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gp_in_0 (gp_in_s[31:0]),
.gp_out_0 (gp_out_s[31:0]),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.otg_vbusoc (1'b0),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_15 (1'b0),
.rx_clk_in (rx_clk_in),
.rx_data_in (rx_data_in),
.rx_frame_in (rx_frame_in),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o (),
.tdd_sync_i (1'b0),
.tdd_sync_o (),
.tdd_sync_t (),
.tx_clk_out (tx_clk_out),
.tx_data_out (tx_data_out),
.tx_frame_out (tx_frame_out),
.txnrx (txnrx),
.up_enable (gpio_o[47]),
.up_txnrx (gpio_o[48]));
endmodule
// ***************************************************************************
// ***************************************************************************