Lars-Peter Clausen 853342b201 altera: adi_jesd204: Disable FPLL phase alignment mode ... Enabling the phase alignment mode of the FPLL seems to break manual re-calibration, which is required when changing the lane rates. The calibration seems to select the wrong VCO frequency band and the PLL no longer locks. Disable phase alignment mode for now, this has a negative effects on deterministic latency, but it is better than not working at all. Waiting for feedback from Altera/Intel on how to make manual re-calibration work in phase alignment mode. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-08-24 17:43:12 +02:00
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adi_jesd204_hw.tcl	altera: adi_jesd204: Disable FPLL phase alignment mode	2017-08-24 17:43:12 +02:00