pluto_hdl_adi/library/util_tdd_sync/util_tdd_sync.v

102 lines
3.7 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
//
// Simple pulse generator for TDD control
// The module has two modes. In function of the state of sync_mode,
// the syncronization signal (sync_out) can get its value from an external
// source or from its internal generator.
//
`timescale 1ns/1ps
module util_tdd_sync #(
parameter TDD_SYNC_PERIOD = 100000000) (
input clk,
input rstn,
input sync_mode,
input sync_in,
output reg sync_out);
reg sync_mode_d1 = 1'b0;
reg sync_mode_d2 = 1'b0;
wire sync_internal;
wire sync_external;
// pulse generator
util_pulse_gen #(
.PULSE_PERIOD(TDD_SYNC_PERIOD)
)
i_tdd_sync (
.clk (clk),
.rstn (rstn),
.pulse (sync_internal)
);
// synchronization logic
always @(posedge clk) begin
if(rstn == 1'b0) begin
sync_mode_d1 <= 1'b0;
sync_mode_d2 <= 1'b0;
end else begin
sync_mode_d1 <= sync_mode;
sync_mode_d2 <= sync_mode_d1;
end
end
// output logic
assign sync_external = sync_in;
always @(posedge clk) begin
if(rstn == 1'b0) begin
sync_out <= 1'b0;
end else begin
sync_out <= (sync_mode_d2 == 1'b0) ? sync_internal : sync_external;
end
end
endmodule