Lars-Peter Clausen 09ffe42603 ad_lvds_in: Allow to disable IDELAY ... The IDELAY is not always required, but it eats up power when instantiated. Allow to disable it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-04-18 12:17:39 +02:00
..
ad_cmos_clk.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
ad_cmos_in.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
ad_cmos_out.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
ad_iobuf.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
ad_lvds_clk.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
ad_lvds_in.v	ad_lvds_in: Allow to disable IDELAY	2017-04-18 12:17:39 +02:00
ad_lvds_out.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
ad_mmcm_drp.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
ad_mul.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
ad_rst_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00
ad_serdes_clk.v	ad_serdes_clk: allow for single ended clock input, made BUFR_DIVIDE configurable	2017-04-18 12:17:39 +02:00
ad_serdes_in.v	ad_serdes: SERDES_FACTOR handover missing	2016-10-10 16:38:42 +03:00
ad_serdes_out.v	ad_serdes_out: allow selection between DDR/SDR configuration and output single ended data	2017-04-18 12:17:39 +02:00
up_clock_mon_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00
up_xfer_cntrl_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00
up_xfer_status_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00