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altera
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altera- infer latest versions
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2017-05-12 13:40:14 -04:00 |
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axi_ad5766
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axi_ad5766: Add missing ports to up_dac_common instance
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2017-05-11 17:25:31 +03:00 |
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axi_ad6676
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Remove duplicare wire declaration
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2017-05-16 19:35:24 +03:00 |
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axi_ad7616
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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axi_ad9122
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Add missing ad_serdes_out interface ports
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2017-05-16 19:35:24 +03:00 |
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axi_ad9144
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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axi_ad9152
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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axi_ad9162
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axi dac cores: Add missing ports to up_dac_common instance
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2017-05-12 13:37:34 +03:00 |
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axi_ad9234
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axi adc cores: Add missing ports to up_adc_common instance
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2017-05-12 13:39:05 +03:00 |
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axi_ad9250
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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axi_ad9265
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Remove duplicare wire declaration
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2017-05-16 19:35:24 +03:00 |
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axi_ad9361
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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axi_ad9371
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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axi_ad9434
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axi adc cores: Add missing ports to up_adc_common instance
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2017-05-12 13:39:05 +03:00 |
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axi_ad9467
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axi adc cores: Add missing ports to up_adc_common instance
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2017-05-12 13:39:05 +03:00 |
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axi_ad9625
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axi adc cores: Add missing ports to up_adc_common instance
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2017-05-12 13:39:05 +03:00 |
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axi_ad9643
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Remove duplicare wire declaration
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2017-05-16 19:35:24 +03:00 |
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axi_ad9652
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Remove duplicare wire declaration
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2017-05-16 19:35:24 +03:00 |
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axi_ad9671
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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axi_ad9680
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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axi_ad9684
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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axi_ad9739a
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Add missing ad_serdes_out interface ports
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2017-05-16 19:35:24 +03:00 |
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axi_ad9963
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axi_ad9963: Update constraints as adc_common and dac_common paths have been renamed
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2017-05-15 18:59:09 +03:00 |
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axi_adc_decimate
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axi_adc_decimate/cic_decim: Fix clk_enable warning
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2017-05-16 19:35:24 +03:00 |
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axi_adc_trigger
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axi_adc_trigger: Reduce AXI address width
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2017-04-18 12:17:41 +02:00 |
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axi_clkgen
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axi_clkgen: Propagate clock settings to output pins
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2017-04-20 20:36:33 +02:00 |
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axi_dac_interpolate
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hdlmake updates
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2017-04-25 15:46:26 -04:00 |
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axi_dmac
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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axi_fmcadc5_sync
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fmcadc5-sync: added a convenience timer
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2017-05-11 12:39:39 -04:00 |
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axi_generic_adc
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axi adc cores: Add missing ports to up_adc_common instance
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2017-05-12 13:39:05 +03:00 |
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axi_gpreg
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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axi_hdmi_rx
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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axi_hdmi_tx
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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axi_i2s_adi
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library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase
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2017-04-18 12:17:41 +02:00 |
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axi_intr_monitor
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updated makefiles
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2016-12-09 23:06:41 +02:00 |
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axi_logic_analyzer
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axi_logic_analyzer: Reduce AXI address width
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2017-04-18 12:17:40 +02:00 |
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axi_mc_controller
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library: Delete all adi_ip_constraint process call
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2017-04-06 12:36:47 +03:00 |
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axi_mc_current_monitor
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axi adc cores: Add missing ports to up_adc_common instance
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2017-05-12 13:39:05 +03:00 |
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axi_mc_speed
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axi adc cores: Add missing ports to up_adc_common instance
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2017-05-12 13:39:05 +03:00 |
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axi_rd_wr_combiner
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hdlmake updates
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2017-04-25 15:46:26 -04:00 |
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axi_spdif_rx
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library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase
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2017-04-18 12:17:41 +02:00 |
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axi_spdif_tx
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library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase
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2017-04-18 12:17:41 +02:00 |
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axi_usb_fx3
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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cn0363
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updated makefiles
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2016-12-09 23:06:41 +02:00 |
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common
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up_dac_common: rename internal signals
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2017-05-15 18:58:26 +03:00 |
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cordic_demod
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updated makefiles
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2016-12-09 23:06:41 +02:00 |
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interfaces
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interfaces- remove channel based pll reset
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2016-11-22 11:34:29 -05:00 |
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prcfg
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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scripts
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version check- change to critical warning
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2017-05-12 09:51:48 -04:00 |
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spi_engine
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spi_engine_offload: Add a CDC module for trigger reception
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2017-05-04 12:14:06 +03:00 |
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util_adcfifo
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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util_axis_fifo
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library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase
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2017-04-18 12:17:41 +02:00 |
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util_axis_resize
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updated makefiles
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2016-12-09 23:06:41 +02:00 |
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util_bsplit
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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util_ccat
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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util_cic
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hdlmake updates
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2017-04-25 15:46:26 -04:00 |
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util_clkdiv
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hdlmake: Fix util_clkdiv Makefile issue. sort library master Makefile
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2017-04-26 09:58:17 +03:00 |
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util_cpack
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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util_dacfifo
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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util_extract
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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util_fir_dec
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util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero
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2017-03-09 16:33:17 +02:00 |
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util_fir_int
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util_fir_int: Force 1/8 filter input data rate
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2017-05-16 19:35:24 +03:00 |
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util_gmii_to_rgmii
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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util_i2c_mixer
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updated makefiles
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2016-12-09 23:06:41 +02:00 |
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util_mfifo
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hdlmake updates
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2017-04-25 15:46:26 -04:00 |
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util_pmod_adc
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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util_pmod_fmeter
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all: Update verilog files to verilog-2001
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2017-04-13 11:59:55 +03:00 |
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util_pulse_gen
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util_pulse_gen: Add Makefile
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2017-04-27 11:28:25 +03:00 |
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util_rfifo
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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util_sigma_delta_spi
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updated makefiles
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2016-12-09 23:06:41 +02:00 |
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util_tdd_sync
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util_tdd_sync: add missing ports
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2017-05-16 19:35:24 +03:00 |
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util_upack
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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util_var_fifo
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hdlmake updates
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2017-04-25 15:46:26 -04:00 |
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util_wfifo
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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xilinx
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altera- default to latest version
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2017-05-12 13:25:17 -04:00 |
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Makefile
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hdlmake.pl updates
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2017-05-04 13:59:47 -04:00 |
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