164 lines
5.6 KiB
Verilog
164 lines
5.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9684_channel #(
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parameter Q_OR_I_N = 0,
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parameter CHANNEL_ID = 0,
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parameter DATAPATH_DISABLE = 0) (
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// adc data interface
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input adc_clk,
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input adc_rst,
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input [27:0] adc_data,
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input [27:0] adc_data_q,
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input adc_or,
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// channel interface
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output [31:0] adc_dfmt_data,
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output adc_valid,
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output adc_enable,
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output up_adc_pn_err,
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output up_adc_pn_oos,
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output up_adc_or,
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// up interface
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input up_clk,
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input up_rstn,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack);
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// internal signals
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wire adc_pn_oos_s;
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wire adc_pn_err_s;
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wire adc_dfmt_enable_s;
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wire adc_dfmt_type_s;
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wire adc_dfmt_se_s;
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wire [ 1:0] adc_dfmt_valid_s;
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wire [ 3:0] adc_pnseq_sel_s;
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// instantiations
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axi_ad9684_pnmon i_pnmon (
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.adc_clk (adc_clk),
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.adc_data (adc_data),
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.adc_pn_oos (adc_pn_oos_s),
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.adc_pn_err (adc_pn_err_s),
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.adc_pnseq_sel (adc_pnseq_sel_s));
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genvar n;
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generate
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for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1
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ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
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.clk (adc_clk),
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.valid (1'b1),
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.data (adc_data[n*14+13:n*14]),
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.valid_out (adc_dfmt_valid_s[n]),
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.data_out (adc_dfmt_data[n*16+15:n*16]),
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.dfmt_enable (adc_dfmt_enable_s),
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.dfmt_type (adc_dfmt_type_s),
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.dfmt_se (adc_dfmt_se_s));
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end
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endgenerate
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assign adc_valid = adc_dfmt_valid_s[0] | adc_dfmt_valid_s[1];
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up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_enable (adc_enable),
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.adc_iqcor_enb (),
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.adc_dcfilt_enb (),
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.adc_dfmt_se (adc_dfmt_se_s),
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.adc_dfmt_type (adc_dfmt_type_s),
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.adc_dfmt_enable (adc_dfmt_enable_s),
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.adc_dcfilt_offset (),
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.adc_dcfilt_coeff (),
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.adc_iqcor_coeff_1 (),
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.adc_iqcor_coeff_2 (),
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.adc_pnseq_sel (adc_pnseq_sel_s),
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.adc_data_sel (),
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.adc_pn_err (adc_pn_err_s),
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.adc_pn_oos (adc_pn_oos_s),
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.adc_or (adc_or),
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.up_adc_pn_err (up_adc_pn_err),
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.up_adc_pn_oos (up_adc_pn_oos),
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.up_adc_or (up_adc_or),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_decimation_m (),
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.up_usr_decimation_n (),
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.adc_usr_datatype_be (1'b0),
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.adc_usr_datatype_signed (1'b1),
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.adc_usr_datatype_shift (8'd0),
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.adc_usr_datatype_total_bits (8'd16),
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.adc_usr_datatype_bits (8'd16),
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.adc_usr_decimation_m (16'd1),
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.adc_usr_decimation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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