118 lines
4.1 KiB
Verilog
118 lines
4.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
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module ad_csc_1 #(
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parameter DELAY_DATA_WIDTH = 16) (
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// data
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input clk,
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input [DW:0] sync,
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input [23:0] data,
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// constants
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input [16:0] C1,
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input [16:0] C2,
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input [16:0] C3,
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input [24:0] C4,
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// sync is delay matched
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output [DW:0] csc_sync_1,
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output [ 7:0] csc_data_1);
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localparam DW = DELAY_DATA_WIDTH - 1;
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// internal wires
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wire [24:0] data_1_m_s;
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wire [24:0] data_2_m_s;
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wire [24:0] data_3_m_s;
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wire [DW:0] sync_3_m_s;
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// c1*R
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ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c1 (
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.clk (clk),
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.data_a (C1),
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.data_b (data[23:16]),
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.data_p (data_1_m_s),
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.ddata_in (1'd0),
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.ddata_out ());
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// c2*G
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ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c2 (
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.clk (clk),
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.data_a (C2),
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.data_b (data[15:8]),
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.data_p (data_2_m_s),
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.ddata_in (1'd0),
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.ddata_out ());
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// c3*B
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ad_csc_1_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_c3 (
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.clk (clk),
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.data_a (C3),
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.data_b (data[7:0]),
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.data_p (data_3_m_s),
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.ddata_in (sync),
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.ddata_out (sync_3_m_s));
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// sum + c4
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ad_csc_1_add #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_add_c4 (
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.clk (clk),
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.data_1 (data_1_m_s),
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.data_2 (data_2_m_s),
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.data_3 (data_3_m_s),
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.data_4 (C4),
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.data_p (csc_data_1),
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.ddata_in (sync_3_m_s),
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.ddata_out (csc_sync_1));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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