Lars-Peter Clausen 7a53b99b8b daq2: zc706: Increase DAC FIFO size ... Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is quite a limiting size for practical applications. Increase the size to 1MB to allow loading larger waveforms. In this configuration the DAC FIFO will use half of the available BRAM cells in the FPGA. This still leaves quite a few BRAMs available for user application logic added to the design. If a user design should run out of BRAMs nevertheless they can reduce the FIFO size, if not required by the application, to free up some cells. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-04-28 12:29:01 +02:00
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Makefile	make updates	2017-03-20 16:05:18 -04:00
system_bd.tcl	daq2: zc706: Increase DAC FIFO size	2017-04-28 12:29:01 +02:00
system_constr.xdc	daq2- adxcvr version	2016-07-21 16:09:33 -04:00
system_project.tcl	file renamed; sed output; fingers crossed	2017-02-22 15:56:37 -05:00
system_top.v	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00